Abstract: A digital phase lock loop circuit with reduced jitter at the output is disclosed. The digital phase lock loop circuit includes a phase frequency detector that determines a phase difference between a feedback signal and a reference frequency signal to generate an error signal indicative of the phase difference. A numerically controlled oscillator generates a first oscillator output signal with a frequency proportional to the error signal and a second oscillator output signal indicative of jitter of the first oscillator output signal in reference to the reference frequency signal. A phase accuracy extender determines a delay amount from the second oscillator output signal and delays the first oscillator output signal by the delay amount to generate a phase-enhanced output signal with edges aligned with one of a plurality of reference clock signals.

Abstract: A modification of a control loop of a primary side sensing power control system that uses a different and unique relationship to accomplish the constant current control while attenuating the affects of a ripple voltage.

Abstract: The present invention is a system and a method that uses primary side sensing to regulate the output voltage at a cable end without any remote sensing of cable connections back from the load. This is accomplished by approximating the current from the control voltage in the control loop through the relationship that defines the Ton time in terms of the control voltage Vc. Once the approximation of the output current is known, it is multiplied by a known fixed cable resistance, and this value is subtracted from the feedback sensor output before it is subtracted from the digital reference. This forces the regulator to raise the output voltage by the amount of drop across the cable, causing the output of the cable to be maintained at the targeted regulation point.

Abstract: A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip.

Abstract: A radar system testing apparatus for use in evaluating radar performance of terrain following, forward looking radars, generally installed in the nose of military aircraft. The operator inputs the antenna position and rotational arc limits desired which are converted into reference voltages and compared to the antenna's true position by a logic comparator network. When the true position is within the operator's selected window, and the radar system inputs a trigger signal to indicate transmitter firing, the logic network will respond with a spiked waveform. This waveform traverses two consecutive one shot multivibrators with appropriate controls to vary the width of the resultant output pulses. By controlling the size of the pulses, the operator effectively selects a variety of target ranges and target widths for testing purposes. These controlled pulses are fed back into the radar system where they generate a simulated target return for evaluating the performance of the radar system under known conditions.