Patents by Inventor John W. Osenbach

John W. Osenbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180131157
    Abstract: Methods, systems, and apparatus, including a laser including a layer having first and second regions, the first region including a void; a mirror section provided on the layer, the mirror section including a waveguide core, at least part of the waveguide core is provided over at least a portion of the void; a first grating provided on the waveguide core; a first cladding layer provided between the layer and the waveguide core and supported by the second region of the layer; a second cladding layer provided on the waveguide core; and a heat source configured to change a temperature of at least one of the waveguide core and the grating, where an optical mode propagating in the waveguide core of the mirror section does not incur substantial loss due to interaction with portions of the mirror section above and below the waveguide core.
    Type: Application
    Filed: January 9, 2018
    Publication date: May 10, 2018
    Inventors: Peter W. Evans, Mingzhi Lu, Fred A. Kish, JR., Vikrant Lal, Scott Corzine, John W. Osenbach, Jin Yan
  • Publication number: 20180131159
    Abstract: Methods, systems, and apparatus, including a laser including a layer having first and second regions, the first region including a void; a mirror section provided on the layer, the mirror section including a waveguide core, at least part of the waveguide core is provided over at least a portion of the void; a first grating provided on the waveguide core; a first cladding layer provided between the layer and the waveguide core and supported by the second region of the layer; a second cladding layer provided on the waveguide core; and a heat source configured to change a temperature of at least one of the waveguide core and the grating, where an optical mode propagating in the waveguide core of the mirror section does not incur substantial loss due to interaction with portions of the mirror section above and below the waveguide core.
    Type: Application
    Filed: January 9, 2018
    Publication date: May 10, 2018
    Inventors: Peter W. Evans, Mingzhi Lu, Fred A. Kish, JR., Vikrant Lal, Scott Corzine, John W. Osenbach, Jin Yan
  • Publication number: 20180131158
    Abstract: Methods, systems, and apparatus, including a laser including a layer having first and second regions, the first region including a void; a mirror section provided on the layer, the mirror section including a waveguide core, at least part of the waveguide core is provided over at least a portion of the void; a first grating provided on the waveguide core; a first cladding layer provided between the layer and the waveguide core and supported by the second region of the layer; a second cladding layer provided on the waveguide core; and a heat source configured to change a temperature of at least one of the waveguide core and the grating, where an optical mode propagating in the waveguide core of the mirror section does not incur substantial loss due to interaction with portions of the mirror section above and below the waveguide core.
    Type: Application
    Filed: January 9, 2018
    Publication date: May 10, 2018
    Inventors: Peter W. Evans, Mingzhi Lu, Fred A. Kish, JR., Vikrant Lal, Scott Corzine, John W. Osenbach, Jin Yan
  • Patent number: 9784933
    Abstract: A device may include a first substrate. The device may include an optical source. The optical source may generate light when a voltage or current is applied to the optical source. The optical source may be being provided on a first region of the first substrate. The device may include a second substrate. A second region of the second substrate may form a cavity with the first region of the first substrate. The optical source may extend into the cavity. The device may include an optical interconnect. The optical interconnect may be provided on or in the second substrate and outside the cavity. The optical interconnect may be configured to receive the light from the optical source.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: October 10, 2017
    Assignee: Infinera Corporation
    Inventors: John W. Osenbach, Timothy Butrie, Fred A. Kish, Jr., Michael Reffle
  • Publication number: 20170194310
    Abstract: Methods, systems, and apparatus, including a photonic integrated circuit package, including a photonic integrated circuit chip, including an active optical element; an electrode configured to receive an electrical signal; a ground electrode; and a bond contact electrically coupled to the electrode; and an ASIC chip including circuitry configured to provide the electrical signal; and a bond contact that is electrically coupled to the circuitry; an bridge chip bonded to at least a portion of the photonic integrated circuit chip and at least a portion of the ASIC chip.
    Type: Application
    Filed: January 4, 2017
    Publication date: July 6, 2017
    Inventors: Peter W. Evans, John W. Osenbach, Fred A. Kish, JR., Jiaming Zhang, Miguel Iglesias Olmedo, Maria Anagnosti
  • Publication number: 20170194308
    Abstract: Methods, systems, and apparatus, including a photonic integrated circuit package, including a photonic integrated circuit chip, including multiple electrodes configured to receive the electrical signal, where at least one characteristics of a segment of the traveling wave active optical element is changed based on the electrical signal received by a corresponding electrode of the multiple electrodes; a ground electrode; and multiple bond contacts; and an interposer bonded to at least a portion of the photonic integrated circuit chip, the interposer including a conductive trace formed on a surface of the interposer, the conductive trace electrically coupled to a source of the electrical signal; a ground trace; and multiple conductive vias electrically coupled to the conductive trace, where each conductive via of the multiple conductive vias is bonded with a respective bond contact of the multiple bond contacts of the photonic integrated circuit chip.
    Type: Application
    Filed: January 4, 2017
    Publication date: July 6, 2017
    Inventors: Peter W. Evans, John W. Osenbach, Fred A. Kish, JR., Jiaming Zhang, Miguel Iglesias Olmedo, Maria Anagnosti
  • Publication number: 20170194309
    Abstract: Methods, systems, and apparatus, including a photonic integrated circuit package, including a photonic integrated circuit chip, including a lumped active optical element; an electrode configured to receive an electrical signal, where at least one characteristics of the lumped active optical element is changed based on the electrical signal received by the electrode; a ground electrode; and a bond contact electrically coupled to the electrode; and an interposer bonded to at least a portion of the photonic integrated circuit chip, the interposer including a conductive trace formed on a surface of the interposer, the conductive trace electrically coupled to a source of the electrical signal; a ground trace; and a conductive via bonded with the bond contact of the photonic integrated circuit chip, the conductive via electrically coupled to the conductive trace to provide the electrical signal to the electrode of the photonic integrated circuit chip.
    Type: Application
    Filed: January 4, 2017
    Publication date: July 6, 2017
    Inventors: Peter W. Evans, John W. Osenbach, Fred A. Kish, JR., Jiaming Zhang, Miguel Iglesias Olmedo, Maria Anagnosti
  • Publication number: 20170194764
    Abstract: Methods, systems, and apparatus, including a laser including a layer having first and second regions, the first region including a void; a mirror section provided on the layer, the mirror section including a waveguide core, at least part of the waveguide core is provided over at least a portion of the void; a first grating provided on the waveguide core; a first cladding layer provided between the layer and the waveguide core and supported by the second region of the layer; a second cladding layer provided on the waveguide core; and a heat source configured to change a temperature of at least one of the waveguide core and the grating, where an optical mode propagating in the waveguide core of the mirror section does not incur substantial loss due to interaction with portions of the mirror section above and below the waveguide core.
    Type: Application
    Filed: January 4, 2017
    Publication date: July 6, 2017
    Inventors: Peter W. Evans, Mingzhi Lu, Fred A. Kish, JR., Vikrant Lal, Scott Corzine, John W. Osenbach, Jin Yan
  • Publication number: 20160290734
    Abstract: A method of fabricating a heat pipe may include providing a first material as a body section. The method may include stamping or etching the body section to include the cavity. A portion of the body section may constitute a wall of the cavity. The method may include stamping or etching the wall of the cavity to provide a set of corrugations on a portion of the wall of the cavity. The method may include forming an opening in the wall of the cavity. The method may include attaching a lid over the cavity. The lid constituting at least a portion of a hermetic seal of the cavity. The method may include attaching a cover to the body section approximately adjacent to the opening in the cavity. The method may include attaching a valve to the body section approximately at the opening to the cavity.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 6, 2016
    Inventors: John W. OSENBACH, Jie TANG, S. Eugene MESSENGER, John CORONATI
  • Patent number: 9443821
    Abstract: A method of forming an electronic device, comprising providing a semiconductor substrate having a first contact and an undoped electroplated lead-free solder bump formed on the first contact. The method also comprises providing a device package substrate having a second contact and a doped lead-free solder layer on the second contact comprising a fourth row transition metal dopant. The method further comprises melting the solder bump and the solder layer while the solder layer and the solder bump are in contact, thereby forming a doped solder bump consisting essentially of Sn, one or both of Ag and Cu, and the fourth row transition metal dopant.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: September 13, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Mark Bachman, John W. Osenbach
  • Publication number: 20160178861
    Abstract: A device may include a first substrate. The device may include an optical source. The optical source may generate light when a voltage or current is applied to the optical source. The optical source may be being provided on a first region of the first substrate. The device may include a second substrate. A second region of the second substrate may form a cavity with the first region of the first substrate. The optical source may extend into the cavity. The device may include an optical interconnect. The optical interconnect may be provided on or in the second substrate and outside the cavity. The optical interconnect may be configured to receive the light from the optical source.
    Type: Application
    Filed: April 17, 2015
    Publication date: June 23, 2016
    Inventors: John W. OSENBACH, Timothy Butrie, Fred A. Kish, JR., Michael Reffle
  • Patent number: 9324557
    Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and a first set of die pads on the device are exposed by forming openings of a first diameter in the photoresist. Pillars of the first diameter are formed by electroplating metal onto the exposed die pads. Then a second photoresist deposited over the first photoresist covers the pillars of the first diameter. Openings of a second diameter are formed in the first and second photoresists to expose a second set of die pads. Pillars of the second diameter are formed by electroplating metal onto the exposed die pads. The photoresists are then removed along with conductive layers on the device used as part of the plating process.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: April 26, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Steven D. Cate, John W. Osenbach
  • Publication number: 20150262949
    Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and first openings in the photoresist are formed. Metal layers are formed by electroplating metal into the first openings for a first time period. Then the photoresist is patterned to form second openings having a smaller diameter than the first openings. Narrow pillars are formed by electroplating metal into the second openings for a second time period during which the metal is also added to the metal layers in the first openings to form wide pillars having substantially the same height as the narrow pillars. The photoresist is then removed along with conductive layers on the device used as part of the plating process.
    Type: Application
    Filed: April 23, 2014
    Publication date: September 17, 2015
    Applicant: LSI Corporation
    Inventors: John W. Osenbach, Steven D. Cate
  • Publication number: 20150262950
    Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and a first set of die pads on the device are exposed by forming openings of a first diameter in the photoresist. Pillars of the first diameter are formed by electroplating metal onto the exposed die pads. Then a second photoresist deposited over the first photoresist covers the pillars of the first diameter. Openings of a second diameter are formed in the first and second photoresists to expose a second set of die pads. Pillars of the second diameter are formed by electroplating metal onto the exposed die pads. The photoresists are then removed along with conductive layers on the device used as part of the plating process.
    Type: Application
    Filed: April 23, 2014
    Publication date: September 17, 2015
    Applicant: LSI Corporation
    Inventors: Steven D. Cate, John W. Osenbach
  • Patent number: 9136245
    Abstract: An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad. The device further comprises an intermetallic compound interface located between the bond pad and the wire and a silicon nitride or silicon carbonyl layer covering the intermetallic compound interface.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: September 15, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd
    Inventors: John M. DeLucca, Ronald J. Weachock, Barry J. Dutt, Frank A. Baiocchi, John W. Osenbach
  • Publication number: 20150243617
    Abstract: A bonding pad arrangement and method of bonding a flip-chip semiconductor device to a substrate using copper pillars and solder to join die pads on the flip-chip to substrate pads on the substrate. Each substrate pad has an offset from a respective die pad at specific temperature, the offset for each of the substrate pads is substantially the same, and the offset is determined as a function of the size of the flip-chip device, a difference between a solidification temperature of the solder and the specific temperature, and a difference between a coefficient of thermal expansion of the flip-chip device and a coefficient of thermal expansion of the substrate. Alternatively, the offset for each of the substrate pads is the above-determined offset scaled as a function of a distance the respective die pad is from the centroid of the device.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 27, 2015
    Applicant: LSI Corporation
    Inventors: John W. Osenbach, Suzanne M. Emerich, David Crouthamel, Steven D. Cate
  • Publication number: 20150243534
    Abstract: A bonding apparatus and method of bonding copper bond wires to bond pads on an integrated circuit devices attached to a substrate. A heater block heats the devices and substrate prior to and during wire bonding. A clamp presses the substrate down onto the heater block during wire bonding and thereby forms a region of the substrate isolated from the remainder of the substrate. A bonder head creates ball bonds as it attaches one end of the bond wires to the bond pads on the devices within the isolated region. The bonder head also attaches the other end of the bond wires to substrate pads adjacent the devices being wire bonded. To prevent corrosion of the ball bonds, a gas source floods the substrate and the attached devices that have not yet wire bonded with a purge gas while the heater block heats the substrate and the attached devices.
    Type: Application
    Filed: April 15, 2014
    Publication date: August 27, 2015
    Applicant: LSI Corporation
    Inventors: John W. Osenbach, BeiQi Wang, Steven Lowell Haehn, Mintra Veeranarong
  • Publication number: 20150214130
    Abstract: A method is provided. The method includes providing an integrated circuit having a substrate. The method also includes locating a via within the substrate. The method further includes connecting the via to a corresponding heat spreader via. The corresponding heat spreader via may pass through a thermally conductive core of a heat spreader.
    Type: Application
    Filed: April 3, 2015
    Publication date: July 30, 2015
    Inventors: Mark A. Bachman, John W. Osenbach, Sailesh M. Merchant
  • Patent number: 9054064
    Abstract: A heat spreader that is configured to be attached to an integrated circuit substrate. The heat spreader includes a thermally conductive core and a heat spreader via that passes through the thermally conductive core. A connection point of the thermally conductive core is configured to form a solder connection to an integrated circuit substrate plug.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: June 9, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Mark A Bachman, John W Osenbach, Sailesh M Merchant
  • Publication number: 20140349475
    Abstract: An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 27, 2014
    Applicant: LSI Corporation
    Inventors: John M. DeLucca, Ronald J. Weachock, Barry J. Dutt, Frank A. Baiocchi, John W. Osenbach