Abstract: Various embodiments of the disclosed subject matter provide systems, methods, architectures, mechanisms, apparatus, computer implemented method and/or frameworks configured for guaranteeing that a payload portion of every data packet provided to a secure/encrypted output port of a processor such as a microprocessor is encrypted.

Abstract: Various embodiments of the disclosed subject matter provide systems, methods, architectures, mechanisms, apparatus, computer implemented method and/or frameworks configured for guaranteeing that a payload portion of every data packet provided to a secure/encrypted output port of a processor such as a microprocessor is encrypted.

Abstract: Apparatus and method for a ring oscillator based random number generator with intentional startup delays timed for each ring to provide a uniform initial spreading of the ring oscillator transition edges. This invention adds a controlled incremental delay in the startup of each individual ring within the ring oscillator random number generator. Typically the delay units used in the ring oscillators themselves can be used to get a course delay between the start times of each ring. A subset of the rings start up with a particular course delay and different fine delays such that the transition edges of all the rings are spread out over the oscillation period. This spreading of the transition edges ensures the output of the random number generator are not a predictable sequence of ones and zeros based on a simultaneous startup of all rings at the same time.

Abstract: Apparatus and method for obscuring round 1 power consumption of hardware implementation of the Advanced Encryption Standard (AES) algorithm. Additional hardware circuitry will provide consistent power consumption during round 1 of the AES algorithm. This prevents the opportunity to determine the AES key value during a side channel power attack.

Abstract: Apparatus and method for obscuring round 1 power consumption of hardware implementation of the AES algorithm. By simultaneously executing a processor floating point operation while executing round 1 of the AES algorithm power consumption of the AddRoundKey transformation is obscured. This prevents the opportunity to determine the AES key value during a side channel power attack.

Abstract: Apparatus and method for a ring oscillator based random number generator with intentional startup delays timed for each ring to provide a uniform initial spreading of the ring oscillator transition edges. This invention adds a controlled incremental delay in the startup of each individual ring within the ring oscillator random number generator. Typically the delay units used in the ring oscillators themselves can be used to get a course delay between the start times of each ring. A subset of the rings start up with a particular course delay and different fine delays such that the transition edges of all the rings are spread out over the oscillation period. This spreading of the transition edges ensures the output of the random number generator are not a predictable sequence of ones and zeros based on a simultaneous startup of all rings at the same time.

Abstract: Apparatus for glitch-free switching between two clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters provides the ability to shut all clocks off for a period of time equal to the longest clock period. By combining the clocks with an OR gate and gating all clocks off before switching from one clock to another, a glitch-free train of clock pulses can be created from individual clock inputs. Since clock glitches can cause erratic behavior in integrated circuits, this invention allows one to switch between different (unrelated) clocks without causing erratic behavior.

Abstract: Apparatus and method for obscuring round 1 power consumption of hardware implementation of the AES algorithm. By simultaneously executing a processor floating point operation while executing round 1 of the AES algorithm power consumption of the AddRoundKey transformation is obscured. This prevents the opportunity to determine the AES key value during a side channel power attack.

Abstract: Apparatus and method for obscuring round 1 power consumption of hardware implementation of the Advanced Encryption Standard (AES) algorithm. Additional hardware circuitry will provide consistent power consumption during round 1 of the AES algorithm. This prevents the opportunity to determine the AES key value during a side channel power attack.

Abstract: Apparatus for glitch-free switching between two clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters provides the ability to shut all clocks off for a period of time equal to the longest clock period. By combining the clocks with an OR gate and gating all clocks off before switching from one clock to another, a glitch-free train of clock pulses can be created from individual clock inputs. Since clock glitches can cause erratic behavior in integrated circuits, this invention allows one to switch between different (unrelated) clocks without causing erratic behavior.