Patents by Inventor John William Kay

John William Kay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11957124
    Abstract: A disposable set of components for an organ perfusion system comprising a fluid supply duct for supplying fluid to the organ, a fluid removal duct for removing fluid from the organ, and a surrogate organ removably connected between the fluid supply duct and the fluid removal duct so as to form a fluid circuit, so that fluid can be circulated in the circuit in preparation for connection of the organ.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 16, 2024
    Assignee: ORGANOX LIMITED
    Inventors: Stuart Brian William Kay, David George Robinson, Philip David Canner, Peter Alan Salkus, Leslie James Russell, Peter John Friend, Constantin C. Coussios
  • Publication number: 20240055218
    Abstract: A charged particle beam writing apparatus according to one aspect of the present invention includes an electrode configured to deflect a charged particle beam, an amplifier configured to apply a deflection potential to the electrode, a diagnostic circuit configured to diagnose the amplifier, a switching circuit arranged between an output of the amplifier and the electrode, and configured to switch the output of the amplifier between the electrode and the diagnostic circuit, an electron optical system configured to irradiate a target object with the charged particle beam deflected by being applied with the deflection potential by the amplifier, a column configured to include therein the electrode and the electron optical system, a first coaxial cable configured to connect an output side of the amplifier with the switching circuit, a second coaxial cable configured to connect the electrode with the switching circuit, a third coaxial cable configured to connect the output side of the amplifier with the diagnosti
    Type: Application
    Filed: December 9, 2021
    Publication date: February 15, 2024
    Applicants: NuFlare Technology, Inc., NuFlare Technology America, Inc.
    Inventors: Yasuo SENGOKU, Yoshikuni GOSHIMA, John William KAY, Chising LAI
  • Patent number: 7898447
    Abstract: A digital-to-analog converter (DAC)/amplifier testing system for use in an electron-beam (e-beam) mask writer, the e-beam mask writer including a plurality of DAC/amplifier circuits to output analog voltage signals, each DAC/amplifier circuit having a first output terminal and a second output terminal, the first output terminals of the plurality of DAC/amplifier circuits being respectively coupled to deflection plates of the e-beam mask writer to provide the output analog voltages as deflection voltages, is provided. The testing system including a summation circuit to sum voltage signals and to output a summation signal indicating the sum of the received analog voltage signals and an analyzer circuit to digitize the summation signal and to detect to compare the digitized summation signal with an error tolerance range to detect whether at least one of the DAC/amplifier circuits is experiencing an operating error.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: March 1, 2011
    Assignee: NuFlare Technology, Inc.
    Inventors: Yoshikuni Goshima, Seiichi Tsuchiya, Yoshimasa Sanmiya, John William Kay, Chising Lai
  • Publication number: 20110012617
    Abstract: A digital-to-analog converter (DAC)/amplifier testing system for use in an electron-beam (e-beam) mask writer, the e-beam mask writer including a plurality of DAC/amplifier circuits to output analog voltage signals, each DAC/amplifier circuit having a first output terminal and a second output terminal, the first output terminals of the plurality of DAC/amplifier circuits being respectively coupled to deflection plates of the e-beam mask writer to provide the output analog voltages as deflection voltages, is provided. The testing system including a summation circuit to sum voltage signals and to output a summation signal indicating the sum of the received analog voltage signals and an analyzer circuit to digitize the summation signal and to detect to compare the digitized summation signal with an error tolerance range to detect whether at least one of the DAC/amplifier circuits is experiencing an operating error.
    Type: Application
    Filed: July 16, 2009
    Publication date: January 20, 2011
    Inventors: Yoshikuni GOSHIMA, Seiichi Tsuchiya, Yoshimasa Sanmiya, John William Kay, Chising Lai
  • Patent number: 5909658
    Abstract: A pattern data processor system is disclosed that comprises a pattern storage device for storing pattern data, a Redundant Array of Independent Disks (RAID) pattern memory buffer for receiving and temporarily holding the pattern data from the pattern storage device, a shape processor for processing and decoding the pattern data, a shape divider, and a shape generator for generating a shape from the decoded pattern data. The shape processor comprises a programmable gate array device (FPGA) that dynamically decodes different pattern data formats with different decoding schemes, allowing for high speed processing. A Previous Output Shape (POS) Register is also disclosed, which uses information from previous shapes to decompress new shapes, thus allowing for variable length macro and pattern data, and conserving disk space.
    Type: Grant
    Filed: June 18, 1996
    Date of Patent: June 1, 1999
    Assignee: International Business Machines Corporation
    Inventors: Eileen Veronica Clarke, John William Kay, Christine Ann Kostek, Jon Erik Lieberman, Daniel Lee Pierce, Robert Joseph Quickle, John Matthew Safran