Abstract: A method for etching silicon is described incorporating first and second steps of reactive ion etching through a patterned oxide layer in respective atmospheres of HBr, Cl.sub.2 and O.sub.2 and then HBr and O.sub.2 in situ by terminating the first etching step and removing substantially all Cl.sub.2 before continuing with the second step of etching. The invention overcomes the problem of uneven etching of n+ and p+ silicon gates for CMOS transistor logic during the step of simultaneously etching silicon to form sub 0.25 micron gate lengths and vertical sidewalls while stopping on the gate oxide.