Patents by Inventor Johnathan Babb

Johnathan Babb has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pipe lined static router and scheduler for configurable logic system performing simultaneous communications and computation
    Patent number: 5850537
    Abstract: A configurable logic system programmed to model a logic design comprises an array of programmable logic modules each configured to perform a partition block of the logic design and a module interconnect providing connections between the modules. The interconnect enables transmission of global links between the partition blocks of the modules. The modules time division multiplex the global links, with a destination module then demultiplexing the global links allowing the links to pass through to another FPGA. The modules are configured to transmit individual ones of the global links at time intervals determined in response to a ready time of the individual links. The ready times of individual global links are determined in response to receipt of parent global links and signal propagation delays across the modules. A parent of a particular global link is a link that affects a logic value of the global link. The present invention allows computation and communication simultaneously.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: December 15, 1998
    Assignee: Virtual Machine Works, Inc.
    Inventors: Charles W. Selvidge, Anant Agarwal, Johnathan Babb, Matthew L. Dahl
  • Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation
    Patent number: 5659716
    Abstract: A configurable logic system programmed to model a logic design comprises an array of programmable logic modules each configured to perform a partition block of the logic design and a module interconnect providing connections between the modules. The interconnect enables transmission of global links between the partition blocks of the modules. The modules time division multiplex the global links, with a destination module then demultiplexing the global links allowing the links to pass through to another FPGA. The modules are configured to transmit individual ones of the global links at time intervals determined in response to a ready time of the individual links. The ready times of individual global links are determined in response to receipt of parent global links and signal propagation delays across the modules. A parent of a particular global link is a link that affects a logic value of the global link. The present invention allows computation and communication simultaneously.
    Type: Grant
    Filed: November 23, 1994
    Date of Patent: August 19, 1997
    Assignee: Virtual Machine Works, Inc.
    Inventors: Charles W. Selvidge, Anant Agarwal, Johnathan Babb, Matthew L. Dahl