Patents by Inventor Johnathan L. Gossi

Johnathan L. Gossi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Generating access line voltages
    Patent number: 11948622
    Abstract: Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Martin Brox, C. Omar Benitez, Johnathan L. Gossi, Christopher John Kawamura
  • GENERATING ACCESS LINE VOLTAGES
    Publication number: 20230335179
    Abstract: Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.
    Type: Application
    Filed: April 15, 2022
    Publication date: October 19, 2023
    Inventors: Martin Brox, C. Omar Benitez, Johnathan L. Gossi, Christopher John Kawamura
  • Compression method for defect visibility in a memory device
    Patent number: 11347585
    Abstract: Methods, systems, and devices for a compression method for defect visibility in a memory device are described. A memory device may identify one or more errors associated with a set of memory cells of a memory array in the device based on a first set of data associated with the first set of memory cells. The memory device may generate an indication of a location of the one or more errors in the first set of memory cells and compress the first set of data to generate an error flag based on identifying the one or more errors. The memory device may output the error flag and the indication of the location based on generating the error flag and the indication.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jiyun Li, Johnathan L. Gossi
  • COMPRESSION METHOD FOR DEFECT VISIBILITY IN A MEMORY DEVICE
    Publication number: 20220012125
    Abstract: Methods, systems, and devices for a compression method for defect visibility in a memory device are described. A memory device may identify one or more errors associated with a set of memory cells of a memory array in the device based on a first set of data associated with the first set of memory cells. The memory device may generate an indication of a location of the one or more errors in the first set of memory cells and compress the first set of data to generate an error flag based on identifying the one or more errors. The memory device may output the error flag and the indication of the location based on generating the error flag and the indication.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 13, 2022
    Inventors: Jiyun Li, Johnathan L. Gossi