Abstract: A power-on reset (POR) circuit includes a first transistor (MPa) having a source coupled to a first supply voltage (VDD) and a gate coupled to a second supply voltage (GND). A resistor (R0) has a first terminal coupled by a depletion mode transistor (JP0) to the second supply voltage and a second terminal coupled to a drain of the first transistor. A Schmitt trigger (20) has an input coupled to receive a first signal (VTRIGGER) on a conductor (14) coupled to the second terminal of the resistor and a terminal of a capacitor (C0), for producing an output voltage (VO) representative of a power-on reset signal (VPOR) in response to an interruption of the first supply voltage (VDD).

Abstract: In a data acquisition system, digitizing circuitry (2A) is powered up by a control signal (ADC_CONVST), superimposing a glitch (42-1) on a first multiplexed and amplified signal value (VINF) received by the digitizing circuitry. Sampling and holding of the first multiplexed and amplified signal value occurs during a delay provided between the glitch and a beginning of a first A/D conversion of the first multiplexed and amplified signal value to allow settling of the glitch. After the first conversion begins, a second multiplexed and amplified signal value is generated. The digitizing circuitry performs the first A/D conversion during initial settling of the second multiplexed and amplified signal value and then is powered down while the second multiplexed and amplified signal value continues to settle.

Abstract: In a data acquisition system, digitizing circuitry (2A) is powered up by a control signal (ADC_CONVST), superimposing a glitch (42-1) on a first multiplexed and amplified signal value (VINF) received by the digitizing circuitry. Sampling and holding of the first multiplexed and amplified signal value occurs during a delay provided between the glitch and a beginning of a first A/D conversion of the first multiplexed and amplified signal value to allow settling of the glitch. After the first conversion begins, a second multiplexed and amplified signal value is generated. The digitizing circuitry performs the first A/D conversion during initial settling of the second multiplexed and amplified signal value and then is powered down while the second multiplexed and amplified signal value continues to settle.

Abstract: A power-on reset (POR) circuit includes a first transistor (MPa) having a source coupled to a first supply voltage (VDD) and a gate coupled to a second supply voltage (GND). A resistor (R0) has a first terminal coupled by a depletion mode transistor (JP0) to the second supply voltage and a second terminal coupled to a drain of the first transistor. A Schmitt trigger (20) has an input coupled to receive a first signal (VTRIGGER) on a conductor (14) coupled to the second terminal of the resistor and a terminal of a capacitor (C0), for producing an output voltage (VO) representative of a power-on reset signal (VPOR) in response to an interruption of the first supply voltage (VDD).

Abstract: A circuit for reducing input offset error and improving gain switching speed in a programmable gain amplifier includes a level shifting buffer that senses a signal on a common mode conductor in a differential input stage of an operational amplifier, and shifts the level of that signal up to the level corresponding to a level of an input signal applied to a non-inverting input of the operational amplifier. If a gain select signal is at a first logic level, the voltage produced by the buffer is applied to a gate electrode of one of a plurality of gain switching JFETs coupling a gain network to the inverting input of the operational amplifier, turning that JFET on. If the gain select signal is at a second logic level, the output of the buffer is isolated from the gain switching JFET and a turn off voltage is applied to the gate of the gain switching JFET.

Abstract: A technique for reducing phase shift of a signal passing through a large thin film resistor on an insulating layer includes applying a signal to one terminal of the thin film resistor and also to one end of an underlying doped epitaxial region. The opposite terminal of the thin film resistor is connected to a virtual ground or virtual reference voltage produced by an inverting input of an operational amplifier. The corresponding opposite end of the epitaxial layer is connected to ground or other reference voltage. The voltage gradients produced by currents flowing through both the thin film resistor and the epitaxial layer are equal, so that substantially no incremental charging current flows through capacitance between the thin film resistor and the epitaxial layer. Phase shift of the signal flowing through the thin film resistor is thereby avoided.