Patents by Inventor Johnny Choe

Johnny Choe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6484193
    Abstract: A fully pipelined parallel multiplier with a fast clock cycle. The pipelined parallel multiplier contains three units: a bit-product matrix unit, a reduction unit, and an addition unit. The bit-product matrix is configured to receive two binary numbers, a multiplier and a multiplicand. A bit-product matrix is formed based on these two numbers. The bit-product matrix unit forms a first pipeline stage. The bit-product matrix is latched to the reduction unit using d-type latch circuits. The reduction unit includes a plurality of reduction stages, with each reduction stage acting as a pipeline stage. The reduction unit reduces the matrix down to a two-row matrix. Intermediate results are latched from one stage to the next using d-type latch circuits. The reduction unit also contains a plurality of half-adder and full-adder circuits. The final two-row matrix formed by the reduction unit is then latched to an addition unit.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: November 19, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gwangwoo Johnny Choe, James R. MacDonald
  • Patent number: 5910994
    Abstract: A method (FIGS. 6-8) for detecting and attenuating N feedback frequencies in a digitized signal uses a tree structure containing a plurality of staged filters. In a step (602), an array of digital filters (FIG. 8) having N branches (40) is constructed. The array is arranged in a tree structure with each branch (40) having several stages (42, 44, and 46). Many of the N filters are used simultaneously in multiple different branches of the tree structure thus reducing the total number of filters required to detect all N feedback frequencies. Within each branch, N-1 of the N filters are notch filters, and each of the N- 1 notch filters attenuates the digitized signal at one of the N feedback frequencies. The remaining one filter in each of the N branches is a bandpass filter that passes the remaining of the N feedback frequency. Therefore, each branch of the tree passes a unique feedback frequency absent of all other N-1 feedback frequencies.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: June 8, 1999
    Assignee: Motorola, Inc.
    Inventors: John E. Lane, Dan Hoory, Johnny Choe
  • Patent number: 5717772
    Abstract: Acoustic feedback is removed from an audio signal (50) by digitizing the audio signal (50) to produce a digitized audio signal (54). The digitized audio signal (54) is then filtered with an adaptive bandpass filter (56) to detect the frequency of the acoustic feedback, where the adaptive bandpass falter (56) is aligned with the feedback based on a phase relationship between the input and the output of the adaptive bandpass filter (56). A notch filter (58) is then configured based on the frequency of the acoustic feedback, and the digitized audio signal (54) is filtered with the notch filter (58) to attenuate the feedback. The feedback-attenuated digitized signal (62) is converted to a feedback-attenuated analog signal (70).
    Type: Grant
    Filed: August 7, 1995
    Date of Patent: February 10, 1998
    Assignee: Motorola, Inc.
    Inventors: John E. Lane, Dan Hoory, Johnny Choe