Abstract: Traditionally, constant current source circuits (and, in particular, constant current source circuits that include cascoded current sources) had numerous drawbacks due to parasitic capacitances, especially at higher switching frequencies. Here, however, a constant current source circuit is provided which uses main and replica constant current source circuitry (with buffering therebetween) to counteract the problems created by parasitic capacitances. Thus, with these new circuits, a generally constant current can be generated, regardless of switching frequency.

Abstract: A current source block provided according to an aspect of the present invention provides a substantially constant current even when the provision of the current is switched on and off at different frequencies. The current source block contains a main portion and a replica portion, with each portion having a current source and switches to connect output of the current source to corresponding output nodes. Additional connections are provided to enable the replica portion to counter deviations in the current output of the main portion due to parasitic effects. As a result, the current source block provides a constant current even when switched off/on at different (in particular high) frequencies. Such current source blocks may be used in components such as current steering DACs to obtain a linear response even at high operational frequencies.

Abstract: A stage of a pipelined ADC used as a sub-ADC in a time-interleaved ADC is operated using a first set of clock signals, with a next stage being operated using a second set of clock signals. The first set and second set of clock signals are designed to cause the start of hold phases of the stage to occur earlier than the sample phases of the next stage. In an embodiment, the start of the hold phases is coincident with the end of an immediately preceding sample phase of the stage. As a result, more time is provided for the output of an amplifier used in the stage to settle to a final value, thus permitting use of a low speed amplifier and reduction in power consumption in the interleaved ADC. In an embodiment, the stage corresponds to an earliest stage in the pipelined sub-ADC.

Abstract: An analog to digital converter (ADC) containing an operational amplifier having a first pair of input terminals and a second pair of input terminals, wherein the output varies if the input signals on either of the input terminals pairs is changed in either the sampling phase or a hold phase. Such an operational amplifier is conveniently shared by two stages of a ADC, while reducing power consumption as well as errors.

Abstract: According to an aspect of present invention, a quantizer is provided with reduced power consumption and area. Such a feature is attained by providing the input signal and a reference signal on input terminals of a pre-amplifier, and coupling the differential output terminals of the pre-amplifier to the gate terminal of respective transistors. The drain/source currents of the transistors are provided to a current latch, which generates the comparison result. The latches and transistors are replicated conveniently to interpolate additional reference values. The width to length (W/L) of the channels in each replicated set are set to different values to cause the reference signal to be at corresponding strength.

Abstract: A pipeline ADC implemented with both general charge redistribution stages and flip-around charge redistribution stages. Using the flip-around charge redistribution stages leads to reduced power/area consumption, but could lead to accumulation and propagation of errors. general charge redistribution stages are used to control/contain the errors. As a result, the ADC is implemented to achieve an acceptable bit error and power efficiency combination. According to another aspect of the present invention, the first stage is implemented as a flip-around charge redistribution stage (in combination with general charge redistribution stages in subsequent stages) since there is no accumulation of error from prior stages, and implementing the first stage as a flip-around charge redistribution stage gives maximum advantages in power efficiency.