Patents by Inventor Jon A. Gwin

Jon A. Gwin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080142899
    Abstract: Radiation hardened integrated circuit devices may be fabricated using conventional designs and process, but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. An exemplary BGR structure includes a high-dose buried guard ring (HBGR) layer which is contacted to ground through the backside of the wafer or circuit die, thus forming a Backside BGR (BBGR) structure. In certain embodiments, the starting wafer may be highly doped to reduce the resistance from the HBGR to the back of the wafer, which is then further contacted to ground through the package. The performance of such devices may be further improved by using an electrically conductive adhesive to attach the die and to electrically connect the silicon substrate region to the package's conductive header, substrate, or die attach pad, which in turn is typically connected to one or more package pins/balls.
    Type: Application
    Filed: August 4, 2007
    Publication date: June 19, 2008
    Applicant: SILICON SPACE TECHNOLOGY CORPORATION
    Inventors: Wesley H. Morris, Jon Gwin, Rex Lowther
  • Patent number: 5786605
    Abstract: A semiconductor deposition and oxidation process using a single furnace cycle. The temperature and gas mixture is stabilized inside the furnace prior to introduction of a dopant at a relatively low temperature. The temperature of the chamber is then ramped-up and the dopant is diffused into the wafer in an inert ambient. The temperature is then ramped-up again and oxygen is introduced to produce an oxide layer. The wafers are then removed from the furnace and any residue of the dopant within the chamber is effectively neutralized by introducing a high flow of oxygen.
    Type: Grant
    Filed: August 6, 1997
    Date of Patent: July 28, 1998
    Assignees: Sony Corporation, Sony Electronics Inc
    Inventor: Jon A. Gwin
  • Patent number: 5494852
    Abstract: A semiconductor deposition and oxidation process using a single furnace cycle. The temperature and gas mixture is stabilized inside the furnace prior to introduction of a dopant at a relatively low temperature. The temperature of the chamber is then ramped-up and the dopant is diffused into the wafer in an inert ambient. The temperature is then ramped-up again and oxygen is introduced to produce an oxide layer. The wafers are then removed from the furnace and any residue of the dopant within the chamber is effectively neutralized by introducing a high flow of oxygen.
    Type: Grant
    Filed: July 28, 1993
    Date of Patent: February 27, 1996
    Assignee: Sony Electronics Inc.
    Inventor: Jon A. Gwin
  • Patent number: 5429704
    Abstract: A tool for etching at least one selected area of a silicon dixoide layer on a wafer. The tool includes a container which is partially filled with hydrofluoric (HF) acid. The tool further includes a template having an aperture extending between each selected area and the container. Vapors of the HF acid pass through each aperture to contact and etch each selected area in order to expose a test die on the wafer. An O-ring is associated with each selected area for sealing each of the selected areas from the remaining areas on the silicon dioxide layer such that substantially only the selected areas are etched by the vapors.
    Type: Grant
    Filed: November 16, 1993
    Date of Patent: July 4, 1995
    Assignee: Sony Electronics, Inc.
    Inventors: Charles A. Butler, Jon Gwin
  • Patent number: 5372649
    Abstract: Apparatus for counterweighting a diffusion furnace cantilever arm for processing silicon wafers which has conventional slotted quartz boats for receiving silicon wafers wherein certain substitutes for said conventional quartz boats are constructed so as to be dummy loads which have the weight and dimensions of a filled quartz boat, but in which no silicon wafers are mounted. Other quartz boats have slots for a particular number of silicon wafers, but the remaining portion of the boat does not receive any wafers, and the boat has the weight and dimensions equivalent to a filled quartz boat. By combining the various boats on the cantilever arm a standard weight can be obtained.
    Type: Grant
    Filed: August 30, 1993
    Date of Patent: December 13, 1994
    Assignee: Sony Electronics, Inc.
    Inventor: Jon A. Gwin