Abstract: A method and structure for reducing short circuits in semiconductor devices is disclosed. A three layer interlevel dielectric structure is formed over a semiconductor substrate, which typically comprises a first metallization level, M1. The three layer dielectric includes a first insulator layer, a middle spin-on glass (SOG) layer, and a top second insulator layer. The spin-on glass fills defects in the surface of the first insulator layer created during planarization using chemical-mechanical-polishing (CMP). Prior to deposition of the second insulator, a first via is etched through the SOG film and the first insulator layer to expose a portion of the semiconductor substrate, typically a conductive metal. A conductive metal is deposited into the first via and planarized to form a metal interconnection stud. Because the surface defects are filled and covered with the SOG film, none of the deposited metal enters the defects, and short circuits with the stud are greatly reduced.