Patents by Inventor Jon Aday

Jon Aday has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12009352
    Abstract: Provided herein include various examples of a method for manufacturing aspects of an apparatus, a sensor system. The method may include obtaining a first carrier bonded to an upper surface of the silicon wafer. This wafer includes through silicon vias (TSVs) extended through openings in a passivation stack, with electrical contacts coupled to portions of the TSVs exposed through these openings. The method may include de-bonding the first carrier from the upper surface of the silicon wafer. The method may include dicing the silicon wafer into subsections comprising dies.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: June 11, 2024
    Assignee: Illumina, Inc.
    Inventors: Arvin Emadi, Jon Aday, Ali Agah, Arnaud Rival
  • Publication number: 20240009665
    Abstract: Provided herein include various examples of a flow cell and methods for forming aspects of flow cell. The method may include applying a first adhesive to a substrate. The method may include orienting a die on the first adhesive. The method may also include orienting a package on the first adhesive. The package includes a die and a top surface of the die comprises an active surface and electrical contact points. Surfaces adjacent to the active surface on at least two opposing sides of the active surface form fanout regions for utilization in a fluidic path of the flow cell. The method further may include applying a second adhesive to a part of the package and attaching a lid to the second adhesive to define a fluidic flow-cell cavity below the lid and above a surface comprising the active surface and the fanout regions.
    Type: Application
    Filed: February 1, 2022
    Publication date: January 11, 2024
    Inventors: Ravi BILLA, John WALKER, Arvin EMADI, Jon ADAY, Tara BOZORG-GRAYELI, Ludovic VINCENT, Hai TRAN, Sanket RATHORE
  • Publication number: 20230249176
    Abstract: Provided herein include various examples of a method for manufacturing aspects of flow cell. The method may include performing chemical processes on a surface of the patterned wafer to prepare the surface of the patterned, singulating the wafer into individual dies, orienting each die on a temporary substrate, where the orienting creates spaces between each individual die, and molding a material over the spaces to create a hybrid wafer comprised of glass and molded material. The method may also include bonding two of the hybrid wafers together, forming a bonded wafer stack.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 10, 2023
    Inventors: Jonathan Ziebarth, Jon Aday, Paul Crivelli, Gerald Kreindl, Amit Sharma
  • Publication number: 20220216191
    Abstract: Provided herein include various examples of a method for manufacturing aspects of an apparatus, a sensor system. The method may include obtaining a first carrier bonded to an upper surface of the silicon wafer. This wafer includes through silicon vias (TSVs) extended through openings in a passivation stack, with electrical contacts coupled to portions of the TSVs exposed through these openings. The method may include de-bonding the first carrier from the upper surface of the silicon wafer. The method may include dicing the silicon wafer into subsections comprising dies.
    Type: Application
    Filed: September 26, 2020
    Publication date: July 7, 2022
    Applicant: ILLUMINA, INC.
    Inventors: Arvin EMADI, Jon ADAY, Ali AGAH, Arnaud RIVAL
  • Patent number: 9679855
    Abstract: Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, that is configured with trenches that are dry-etched into a surface of the substrate inside an area defined by scribe lines of the substrate. A crack stop structure is provided for the semiconductor device that includes a polymer dielectric layer coating that fills the trenches with a polymer dielectric material and provides a dielectric layer over the surface of the substrate inside the area. The polymer dielectric layer coating and trenches are configured to reduce cracking or chipping of the substrate in the area defined by scribe lines after cutting.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: June 13, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Jae Sik Lee, Hong Bok We, Dong Wook Kim, Jon Aday