Abstract: A differential amplifier design and bias control technique of particular applicability for low voltage operation in which the threshold voltage of n-channel differential input transistors is controlled using substrate bias in order to allow a wider range of input signal levels. Further disclosed is a technique for controlling the substrate bias of the input transistors of a differential amplifier based on the level of the output of the amplifier in addition to a differential amplifier circuit capable of low voltage operation in which an additional bias current is introduced that enables the output pull-up current to be increased without increasing the pull-down current.

Abstract: A level shifting circuit includes an input node, an output node, a first power supply node, a second power supply node, a third power supply node, an inverter coupled to the first and second power supply nodes having an input coupled to the input node and an output, a transistor having a current path coupled between the output of the inverter an the output node, a first transistor circuit coupled between the first power supply node and the third power supply node having a first input coupled to the output of the inverter, a second input coupled to the output node, and an output, and a second transistor circuit coupled between the output node and the third power supply node having a first input coupled to the output of the first transistor circuit and a second input coupled to the input node.

Abstract: A limited output address register technique for selectively variable write latency in double data rate 2 (DDR2) integrated circuit memory devices providing a reduced number of paths directly connected to the output. A chain of DQ flip-flops is disclosed which is only loaded on valid write address commands but shifts continually thereafter every clock cycle. Since new READ or WRITE commands cannot be issued on successive cycles, at any given point in the chain an address (or state) is valid for at least two cycles. Therefore, a selected point in the register chain can be used to satisfy the requirements for two different latencies. For DDR2, having N write latency cases, only ceil(N/2) access points to the write address output have to be provided thereby saving on-chip area and increasing speed. In a specific embodiment disclosed, DDR1 may also be supported.

Abstract: An integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section in which the architecture is divided into memory sections, depending upon their distance from the address/control generation block. The address and clock information is re-driven between these sections, which effectively serves to add a quantized number of gate delays in the address path between the sections while concomitantly minimizing skew. A corresponding number of gate delays is also added to the “read” data path for each section such that the number of delays in the address/clock path plus the number of delays in the “read” data path is substantially constant.

Abstract: A sorting circuit (140) transfers data between a first group of at least four lines (134) on which the data items are arranged based on their addresses, and a second group of lines (138, WD0R, WD0F, WD1R, WD1F) on which the data items are arranged based on the order in which they are read or written in a burst operation. Six signals (SORT) and their complements are sufficient to control the sorting circuit for both the read and the write operations, and provide both the DDR and the DDR2 functionality.

Abstract: A circuit and method of generating an internal chip clock signal for distribution throughout an integrated circuit in response to an external clock signal includes the steps of generating a minimum width internal clock signal if the width of the external clock signal is less than a predetermined minimum width, generating an internal clock signal having a width substantially equal to the width of the external clock signal if the width of the external clock signal is greater than a predetermined minimum width but less than a predetermined maximum width, and generating a maximum width internal clock signal if the width of the external clock signal is greater than a predetermined maximum width.

Abstract: A latch circuit and method of operation improves the performance of an integrated circuit memory by adding an extra latch into the write data path. The added latch is programmable such that it either is disabled (allowing the transparent flow of data), or enabled (data flow is inhibited by extra clock). In areas of the chip where the address/control information is fast, but the data is slow, the latch is disabled to allow the data to flow as fast as possible. In areas of the chip where the address/control information is slow, but the data is fast, the latch is enabled such that data cannot flow freely and must be gated by clock information.

Abstract: An integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section in which the architecture is divided into memory sections, depending upon their distance from the address/control generation block. The address and clock information is re-driven between these sections, which effectively serves to add a quantized number of gate delays in the address path between the sections while concomitantly minimizing skew. A corresponding number of gate delays is also added to the “read” data path for each section such that the number of delays in the address/clock path plus the number of delays in the “read” data path is substantially constant.

Abstract: A pre-biased voltage level shifting circuit of especial applicability with respect to those integrated circuit devices requiring a technique for converting circuit operation between differing power supply levels. In a representative embodiment, the circuit utilizes feedback to make the switching transistors faster to thereby increase the speed of the level translation of signals based upon two different power supplies.

Abstract: A pre-biased voltage level shifting circuit of especial applicability with respect to those integrated circuit devices requiring a technique for converting circuit operation between differing power supply levels. In a representative embodiment, the circuit utilizes feedback to make the switching transistors faster to thereby increase the speeds of the level translation of signals based upon two different power supplies.

Abstract: A circuit and method of generating an internal chip clock signal for distribution throughout an integrated circuit in response to an external clock signal includes the steps of generating a minimum width internal clock signal if the width of the external clock signal is less than a predetermined minimum width, generating an internal clock signal having a width substantially equal to the width of the external clock signal if the width of the external clock signal is greater than a predetermined minimum width but less than a predetermined maximum width, and generating a maximum width internal clock signal if the width of the external clock signal is greater than a predetermined maximum width.

Abstract: A latch circuit and method of operation improves the performance of an integrated circuit memory by adding an extra latch into the write data path. The added latch is programmable such that it either is disabled (allowing the transparent flow of data), or enabled (data flow is inhibited by extra clock). In areas of the chip where the address/control information is fast, but the data is slow, the latch is disabled to allow the data to flow as fast as possible. In areas of the chip where the address/control information is slow, but the data is fast, the latch is enabled such that data cannot flow freely and must be gated by clock information.

Abstract: A multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output (“I/O”) assignments in an integrated circuit memory device. By using non-uniform blocks of multiple identical sub-arrays, non-uniform assignments of blocks to banks and/or non-uniform assignments of I/Os to blocks, it is possible to optimize the dimensions of the chip and the placement of the I/Os with respect to the package pads. In this manner, the granularity of the building blocks of sub-arrays is improved while the flexibility in I/O assignment is also improved leading to more efficient and flexible chip layouts.

Abstract: An integrated data input sorting and timing circuit for double data rate (“DDR”) dynamic random access memory (“DRAM”) devices in which a sorting of the input data into odd/even is integrated with the necessary timing to allow synchronization with the on-chip Y-clock signal (column address select) without the need to provide separate circuits. In those devices having multiple DQS inputs, any skew between DQS pins is allowed as long as no one DQS pin violates the DQS-to-clock (“DQS-CLK”) skew requirements. The circuit and method of the present invention also allows a write to occur at command +2 cycles (last data + ½). Functionally, both rising and falling data (i.e., data on the rising and falling edges of DQS) is captured by the DQS inputs and presented in parallel to the chips internal write path and data is passed on the falling edge of DQS.

Abstract: A multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output (“I/O”) assignments in an integrated circuit memory device. By using non-uniform blocks of multiple identical sub-arrays, non-uniform assignments of blocks to banks and/or non-uniform assignments of I/Os to blocks, it is possible to optimize the dimensions of the chip and the placement of the I/Os with respect to the package pads. In this manner, the granularity of the building blocks of sub-arrays is improved while the flexibility in I/O assignment is also improved leading to more efficient and flexible chip layouts.

Abstract: An integrated data input sorting and timing circuit for double data rate (“DDR”) dynamic random access memory (“DRAM”) devices in which a sorting of the input data into odd/even is integrated with the necessary timing to allow synchronization with the on-chip Y-clock signal (column address select) without the need to provide separate circuits. In those devices having multiple DQS inputs, any skew between DQS pins is allowed as long as no one DQS pin violates the DQS-to-clock (“DQS-CLK”) skew requirements. The circuit and method of the present invention also allows a write to occur at command +2 cycles (last data +½). Functionally, both rising and falling data (i.e., data on the rising and falling edges of DQS) is captured by the DQS inputs and presented in parallel to the chips internal write path and data is passed on the falling edge of DQS.

Abstract: An arbitration method and circuit for control of double data rate (“DDR”) dynamic random access memory (“DRAM”) device first-in, first-out (“FIFO”) registers which allows the data path of the device to be functional over a wider range of system clock and delay locked loop (“DLL”) clock signal skews. By comparing the system and DLL clocks, the circuit and method of the present invention determines whether the DLL clock should be considered “faster” than the system clock, or “slower.” Functionally, it then attempts to force all cases into the “fast” condition until a determination is made that the amount of advance is now so fast, that data corruption in the pipeline might occur. Only in this case will it force the result to be “slow,” adding 1 cycle to the output control path, and thereby correcting the data flow.

Abstract: An integrated data input sorting and timing circuit for double data rate (“DDR”) dynamic random access memory (“DRAM”) devices in which a sorting of the input data into odd/even is integrated with the necessary timing to allow synchronization with the on-chip Y-clock signal (column address select) without the need to provide separate circuits. In those devices having multiple DQS inputs, any skew between DQS pins is allowed as long as no one DQS pin violates the DQS-to-clock (“DQS-CLK”) skew requirements. The circuit and method of the present invention also allows a write to occur at command +2 cycles (last data+½). Functionally, both rising and falling data (i.e., data on the rising and falling edges of DQS) is captured by the DQS inputs and presented in parallel to the chips internal write path and data is passed on the falling edge of DQS.

Abstract: An integrated data input sorting and timing circuit for double data rate (“DDR”) dynamic random access memory (“DRAM”) devices in which a sorting of the input data into odd/even is integrated with the necessary timing to allow synchronization with the on-chip Y-clock signal (column address select) without the need to provide separate circuits. In those devices having multiple DQS inputs, any skew between DQS pins is allowed as long as no one DQS pin violates the DQS-to-clock (“DQS-CLK”) skew requirements. The circuit and method of the present invention also allows a write to occur at command +2 cycles (last data +½). Functionally, both rising and falling data (i.e., data on the rising and falling edges of DQS) is captured by the DQS inputs and presented in parallel to the chips internal write path and data is passed on the falling edge of DQS.

Abstract: An integrated data input sorting and timing circuit for double data rate (“DDR”) dynamic random access memory (“DRAM”) devices in which a sorting of the input data into odd/even is integrated with the necessary timing to allow synchronization with the on-chip Y-clock signal (column address select) without the need to provide separate circuits. In those devices having multiple DQS inputs, any skew between DQS pins is allowed as long as no one DQS pin violates the DQS-to-clock (“DQS-CLK”) skew requirements. The circuit and method of the present invention also allows a write to occur at command +2 cycles (last data+½). Functionally, both rising and falling data (i.e., data on the rising and falling edges of DQS) is captured by the DQS inputs and presented in parallel to the chips internal write path and data is passed on the falling edge of DQS.