Patents by Inventor Jon C. R. Bennett
Jon C. R. Bennett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9189334Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.Type: GrantFiled: May 8, 2015Date of Patent: November 17, 2015Assignee: VIOLIN MEMORY, INC.Inventor: Jon C. R. Bennett
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Patent number: 9164839Abstract: Storage of digital data in non-volatile media such as NAND FLASH needs to take account of the errors in data retrieved from the memory. The error rate tends to increase with the number of write/erase cycles of a cell of memory and with the time that the data has been stored. To achieve a very low uncorrected bit error rate (UBER) a substantial amount of redundancy data needs to be stored for error correction purposes. A method and apparatus is disclosed where a first redundancy data is represented by a second redundancy data computed from the first redundancy data. The first redundancy data may not be stored and is reconstructed from the stored data using a same generation procedure as previously used. The reconstructed estimate of the first redundancy data is corrected by the second redundancy data, and is used to correct the underlying data.Type: GrantFiled: July 24, 2014Date of Patent: October 20, 2015Assignee: VIOLIN MEMORY INCInventor: Jon C. R. Bennett
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Patent number: 9141302Abstract: A system and method of managing the storage of data in flash memory performs snapshots of the data by maintaining the data at the epoch that the snapshot is performed in the same physical memory location. Data that is modified after the snapshot is then stored to a new physical memory location and referenced to the snapshot location. When a user read operation is performed, the data is read from the original location if the read operation is for the snapshot data. The read operation for dynamic data is performed from the original location if the data has not change since the snapshot epoch, or from the referenced data location if the data has changed since the snapshot epoch. Snapshots are released by dereferencing the original location if the data has been changed since the snapshot epoch.Type: GrantFiled: April 18, 2013Date of Patent: September 22, 2015Assignee: VIOLIN MEMORYInventor: Jon C. R. Bennett
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Publication number: 20150242271Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.Type: ApplicationFiled: May 8, 2015Publication date: August 27, 2015Inventor: Jon C.R. Bennett
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Patent number: 9081713Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.Type: GrantFiled: March 10, 2015Date of Patent: July 14, 2015Assignee: VIOLIN MEMORY, INC.Inventor: Jon C. R. Bennett
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Publication number: 20150178157Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.Type: ApplicationFiled: March 10, 2015Publication date: June 25, 2015Inventor: Jon C.R. Bennett
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Publication number: 20140365726Abstract: A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module. A plurality of groups of controllers may communicate with a switch or with a representative controller so as to coordinate the assignment of global sequence numbers.Type: ApplicationFiled: June 6, 2013Publication date: December 11, 2014Inventors: Jon C.R. Bennett, Daniel C. Biederman, David M. Smith
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Publication number: 20140337687Abstract: Storage of digital data in non-volatile media such as NAND FLASH needs to take account of the errors in data retrieved from the memory. The error rate tends to increase with the number of write/erase cycles of a cell of memory and with the time that the data has been stored. To achieve a very low uncorrected bit error rate (UBER) a substantial amount of redundancy data needs to be stored for error correction purposes. A method and apparatus is disclosed where a first redundancy data is represented by a second redundancy data computed from the first redundancy data. The first redundancy data may not be stored and is reconstructed from the stored data using a same generation procedure as previously used. The reconstructed estimate of the first redundancy data is corrected by the second redundancy data, and is used to correct the underlying data.Type: ApplicationFiled: July 24, 2014Publication date: November 13, 2014Inventor: Jon C.R. Bennett
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Publication number: 20140310483Abstract: A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.Type: ApplicationFiled: April 15, 2013Publication date: October 16, 2014Applicant: VIOLIN MEMORY INC.Inventor: Jon C.R. Bennett
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Patent number: 8832524Abstract: Storage of digital data in non-volatile media such as NAND FLASH needs to take account of the errors in data retrieved from the memory. The error rate tends to increase with the number of write/erase cycles of a cell of memory and with the time that the data has been stored. To achieve a very low uncorrected bit error rate (UBER) a substantial amount of redundancy data needs to be stored for error correction purposes. A method and apparatus is disclosed where a first redundancy data is represented by a second redundancy data computed from the first redundancy data. The first redundancy data may not be stored and is reconstructed from the stored data using a same generation procedure as previously used. The reconstructed estimate of the first redundancy data is corrected by the second redundancy data, and is used to correct the underlying data.Type: GrantFiled: September 21, 2012Date of Patent: September 9, 2014Assignee: Violin Memory, Inc.Inventor: Jon C. R. Bennett
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Publication number: 20140195725Abstract: A system and method of storing data in a semiconductor-type non-volatile memory is described, where a physical storage address of data is made available to a user application such as a file system and where characteristics of the memory system that may be allocated on a physical or a logical basis to a user are separately characterizable as to performance, size, redundancy, or the like. A read request to the memory system may be serviced by accessing the physical address included in the read request rather than using a logical-to-physical address lookup in the memory system. Garbage collection operations may be performed on a virtual-physical-block basis to preserve the relationship between the physical address known to the user and the actual physical location of the data.Type: ApplicationFiled: January 8, 2014Publication date: July 10, 2014Inventor: Jon C.R. Bennett
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Patent number: 8726064Abstract: An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.Type: GrantFiled: April 17, 2006Date of Patent: May 13, 2014Assignee: Violin Memory Inc.Inventor: Jon C. R. Bennett
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Publication number: 20140013048Abstract: In a memory system where memory units may be separated from each other so as to operate substantially independently, the coordination of related memory operations between such units may be by synchronization of an epoch of time and the start of an epoch of time with a common synchronization source. The source may be distributed directly to each of the memory modules of a memory unit, or through an intermediate synchronization circuit of a memory unit that is common to the modules. Where the data is stored as a RAID stripe on a plurality of synchronized modules, the read and write or erase operations performed by the modules may be arranged such that the write operations or erase operations may not substantially affect the ability to promptly read the stored data of a RAID stripe.Type: ApplicationFiled: July 2, 2013Publication date: January 9, 2014Inventors: Daniel C. Biederman, Jon C.R. Bennett
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Publication number: 20130282999Abstract: A system and method of managing the storage of data in flash memory performs snapshots of the data by maintaining the data at the epoch that the snapshot is performed in the same physical memory location. Data that is modified after the snapshot is then stored to a new physical memory location and referenced to the snapshot location. When a user read operation is performed, the data is read from the original location if the read operation is for the snapshot data. The read operation for dynamic data is performed from the original location if the data has not change since the snapshot epoch, or from the referenced data location if the data has changed since the snapshot epoch. Snapshots are released by dereferencing the original location if the data has been changed since the snapshot epoch.Type: ApplicationFiled: April 18, 2013Publication date: October 24, 2013Inventor: Jon C.R. Bennett
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Publication number: 20130282980Abstract: A system and method is described for operating a computer memory system having a plurality of controllers capable of accessing a common set of memory modules. Access to the physical storage of the memory modules may be managed by configuration logical units (LUNs) addressable by the users. The amount of memory associated with each LUN may be managed in units of memory (LMA) from a same free LMA table maintained in each controller of the plurality of controllers. A request for maintenance of a LUN may be received from any user through any controller and results in the association of a free memory area with the LUN, and the remaining controllers perform the same operation. A test for misallocation of a free memory area is performed and when such misallocation occurs, the situation is corrected in accordance with a policy.Type: ApplicationFiled: April 18, 2013Publication date: October 24, 2013Inventor: Jon C.R. Bennett
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Publication number: 20130275660Abstract: A method and system for managing a flash memory system facilitates the use of TRIM or similar operations so as to release physical memory space of logical block addresses that are declared to be deleted by a user file management system. A series of data structures accounts for the levels of indirection used to manage the correspondence between a user logical block address and the physical location of the data in the memory system and to respond to user read and write requests by efficiently determining the current status of the user logical block address in the frame of reference of the memory system and substantially decoupling the TRIM management from the garbage collection and wear leveling operations.Type: ApplicationFiled: April 10, 2013Publication date: October 17, 2013Inventor: Jon C.R. Bennett
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Publication number: 20130262739Abstract: A memory system having a plurality of modules operated so that a group of memory modules may operation in a RAID configuration having an erase hiding property. The RAID groups are mapped to areas of memory in each of the memory modules of the RAID group. More than one RAID group may be mapped to a memory module and the erase operations of the RAID groups coordinated such that the erase operations do not overlap. This may improve the utilization of a bus over which the memory module communicates with the controller. Where a memory module is replaced by a memory module having an increased storage capacity, the additional storage capacity may be mapped to an expanded logical address space.Type: ApplicationFiled: March 13, 2013Publication date: October 3, 2013Inventors: Jon C.R. Bennett, Daniel C. Biederman
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Patent number: 8452929Abstract: A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.Type: GrantFiled: November 18, 2008Date of Patent: May 28, 2013Assignee: Violin Memory Inc.Inventor: Jon C. R. Bennett
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Publication number: 20130080862Abstract: Storage of digital data in non-volatile media such as NAND FLASH needs to take account of the errors in data retrieved from the memory. The error rate tends to increase with the number of write/erase cycles of a cell of memory and with the time that the data has been stored. To achieve a very low uncorrected bit error rate (UBER) a substantial amount of redundancy data needs to be stored for error correction purposes. A method and apparatus is disclosed where a first redundancy data is represented by a second redundancy data computed from the first redundancy data. The first redundancy data may not be stored and is reconstructed from the stored data using a same generation procedure as previously used. The reconstructed estimate of the first redundancy data is corrected by the second redundancy data, and is used to correct the underlying data.Type: ApplicationFiled: September 21, 2012Publication date: March 28, 2013Inventor: Jon C.R. BENNETT
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Publication number: 20130042119Abstract: An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.Type: ApplicationFiled: April 10, 2012Publication date: February 14, 2013Inventor: Jon C.R. Bennett