Abstract: An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.

Abstract: A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

Abstract: A semiconductor device comprising a substrate having a first crystal orientation and an insulating layer overlying the substrate is provided. A plurality of silicon layers are formed overlying the insulating layer. A first silicon layer comprises silicon having the first crystal orientation and a second silicon layer comprises silicon having a second crystal orientation. In addition, a method of forming a semiconductor device providing a silicon-on-insulator structure comprising a substrate with a silicon layer overlying the substrate and a first insulating layer interposed therebetween is provided. An opening is formed in a first region of the silicon-on-insulator structure by removing a portion of the silicon layer and the first insulating layer to expose a portion of the substrate layer. Selective epitaxial silicon is grown in the opening. A second insulating layer is formed in the silicon grown in the opening to provide an insulating layer between the grown silicon in the opening and the substrate.

Abstract: An insulated gate field effect transistor having reduced gate-drain overlap and a method for manufacturing the insulated gate field effect transistor. A gate structure is formed on a major surface of a semiconductor substrate. A source extension region and a drain extension region are formed in a semiconductor material using an angled implant. The source extension region extends under the gate structure, whereas the drain extension region is laterally spaced apart from the gate structure. A source region is formed in the semiconductor substrate and a drain region is formed in the semiconductor substrate, where the source and drain regions are laterally spaced apart from the gate structure. A source-side halo region is formed in the semiconductor substrate adjacent the source extension region.

Abstract: A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

Abstract: An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.

Abstract: A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

Abstract: A semiconductor device comprising a substrate having a first crystal orientation is provided. A first insulating layer overlies the substrate and a plurality of silicon layers overlie the first insulating layer. A first silicon layer comprises silicon having a second crystal orientation and a crystal plane. A second silicon layer comprises silicon having the second crystal orientation and a crystal plane that is substantially orthogonal to the crystal plane of the first silicon layer. Because holes have higher mobility in the (110) plane than the (100) plane, while electrons have higher mobility in (100) plane than the (110) plane, semiconductor device performance can be enhanced by the selection of silicon layers with certain crystal plane orientations. In addition, a method of forming a semiconductor device is provided.

Abstract: A semiconductor device comprising a substrate having a first crystal orientation and an insulating layer overlying the substrate is provided. A plurality of silicon layers are formed overlying the insulating layer. A first silicon layer comprises silicon having the first crystal orientation and a second silicon layer comprises silicon having a second crystal orientation. In addition, a method of forming a semiconductor device providing a silicon-on-insulator structure comprising a substrate with a silicon layer overlying the substrate and a first insulating layer interposed therebetween is provided. An opening is formed in a first region of the silicon-on-insulator structure by removing a portion of the silicon layer and the first insulating layer to expose a portion of the substrate layer. Selective epitaxial silicon is grown in the opening. A second insulating layer is formed in the silicon grown in the opening to provide an insulating layer between the grown silicon in the opening and the substrate.

Abstract: STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 ?. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.

Abstract: A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

Abstract: An insulated gate field effect semiconductor component having a source-side halo region and a method for manufacturing the semiconductor component. A gate structure is formed on a semiconductor substrate. The source-side halo region is formed in the semiconductor substrate. After formation of the source-side halo region, spacers are formed adjacent opposing sides of the gate structure. A source extension region and a drain extension region are formed in the semiconductor substrate using an angled implant. The source extension region extends under the gate structure, whereas the drain extension may extend under the gate structure or be laterally spaced apart from the gate structure. A source region and a drain region are formed in the semiconductor substrate.

Abstract: An insulated gate field effect transistor having differentially doped source-side and drain-side halo regions and a method for manufacturing the transistor. A gate structure is formed on a major surface of a semiconductor substrate. A source-side halo region is proximal the source extension region and a drain-side halo region is proximal the drain extension region, where the drain-side halo region has a higher dopant concentration than the source-side halo region. A source extension region and a drain extension region are formed in a semiconductor material. The source extension region extends under a gate structure, whereas the drain extension region may extend under the gate structure or be laterally spaced apart from the gate structure or be aligned to the gate side adjacent the drain region. A source region is adjacent the source extension region and a drain region is adjacent the drain extension region.

Abstract: A semiconductor structure an a process for its manufacture. First and second gate dielectric layers are formed on a semiconductor substrate between nitride spacers, and a metal gate electrode is formed on the gate dielectric layers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions. The metal gate electrode is aligned using a polysilicon alignment structure, which permits high temperature processing before the metal is deposited.

Abstract: A semiconductor structure and a process for its manufacture. A metal gate electrode is formed on a semiconductor substrate, the gate electrode being between nitride spacers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions.

Abstract: A memory cell assembly includes a substrate, a first electrode, and a second electrode layer. The first electrode is disposed over the substrate and the second electrode layer is disposed over the first electrode. The second electrode layer includes two or more second electrodes. Dielectric material separates the first electrode form the second electrodes and also separates the second electrodes. Each second electrode forms an individual memory cell associated with the first electrode. The memory cell assembly can be made by, first, forming a first electrode over a substrate. A second electrode layer is formed over the first electrode. The second electrode layer includes two or more second electrodes. A dielectric material is formed between the first electrode and the second electrodes and between the second electrodes.

Abstract: One method of making a semiconductor device includes forming a gate electrode on a substrate and forming a spacer on a sidewall of the gate electrode. An active region is then formed in the substrate and adjacent to the spacer, but spaced apart from the gate electrode, using a first dopant material. A halo region is formed in the substrate under the spacer and adjacent to the active region using a second dopant material of a conductivity type different than the first dopant material. The halo region may be formed by implanting the second dopant region into the substrate at an angle substantially less than 90° relative to a surface of the substrate. A portion of the spacer is then removed and a lightly-doped region is formed in the substrate adjacent to the active region and the gate electrode and shallower than the halo region using a third dopant material of a same conductivity type as the first dopant material.

Abstract: A memory cell assembly includes a substrate, a first electrode, and a second electrode layer. The first electrode is disposed over the substrate and the second electrode layer is disposed over the first electrode. The second electrode layer includes two or more second electrodes. Dielectric material separates the first electrode form the second electrodes and also separates the second electrodes. Each second electrode forms an individual memory cell associated with the first electrode. The memory cell assembly can be made by, first, forming a first electrode over a substrate. A second electrode layer is formed over the first electrode. The second electrode layer includes two or more second electrodes. A dielectric material is formed between the first electrode and the second electrodes and between the second electrodes.

Abstract: A process for breaking silicide stringers extending between silicide regions of different active regions on a semiconductor device is provided. Consistent with an exemplary fabrication process, two adjacent silicon active regions are formed on a substrate and a metal layer is formed over the two adjacent silicon active regions. The metal layer is then reacted with the silicon active regions to form a metal silicide on each silicon active region. This silicide reaction also forms silicide stringers extending from each silicon active region. Finally, at least part of each silicide stringer is removed. During the formation of the silicide stringers at least one silicide stringer may be formed which bridges the metal silicide over one of the silicon regions and the metal silicide over the other silicon region. In such circumstances, the removal process may, for example, break the silicide stringer and electrically decouple the two silicon regions.

Abstract: A metal gate electrode formed with high temperature activation of source/drain and LDD implants and a process for manufacture. A polysilicon alignment structure is formed on a silicon substrate. Source/drain regions are formed in alignment with the polysilicon alignment structure, and the alignment structure and the substrate are subjected to a first rapid thermal anneal. LDD implant regions are formed and the alignment structure and the substrate having the LDD regions are subjected to a second rapid thermal anneal. The polysilicon alignment structure is replaced with a metal gate electrode and gate dielectric.