Abstract: A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive material layer. An electrically isolating material layer is formed between the phase change material layer and the energy conversion layer.

Abstract: A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive material layer. An electrically isolating material layer is formed between the phase change material layer and the energy conversion layer.

Abstract: A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The stabilizing solution comprises a non-volatile component, such as non-volatile particles or polymers, which is applied after the photoresist material has been developed. By treating the photoresist with the solution containing a non-volatile component after developing but before drying, the non-volatile component fills the space between adjacent resist patterns and remains on the substrate during drying. The non-volatile component provides structural and mechanical support for the resist to prevent deformation or collapse by liquid surface tension forces.

Abstract: An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.

Abstract: A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode, a resistance variable material over the first electrode, and a first second-electrode over the resistance variable material. The first second-electrode is associated with the first electrode to define a first memory element. Each memory unit further includes a second second-electrode over the resistance variable material. The second-second electrode is associated with the first electrode to define a second memory element.

Abstract: A memory element having a resistance variable material and methods for forming the same are provided. The method includes forming a plurality of first electrodes over a substrate and forming a blanket material stack over the first electrodes. The stack includes a plurality of layers, at least one layer of the stack includes a resistance variable material. The method also includes forming a first conductive layer on the stack and etching the conductive layer and at least one of the layers of the stack to form a first pattern of material stacks. The etched first conductive layer forming a plurality of second electrodes with a portion of the resistance variable material located between each of the first and second electrodes.

Abstract: An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.

Abstract: An imaging method and apparatus is disclosed which improves the depth of field of an image by, in one exemplary embodiment, capturing a plurality of images at respective different focus positions, and combines the images into one image and sharpens the one image. In an alternative exemplary embodiment, a single image is captured while the focus positions change during image capture, and the resulting image is sharpened.

Abstract: A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode, a resistance variable material over the first electrode, and a first second-electrode over the resistance variable material. The first second-electrode is associated with the first electrode to define a first memory element. Each memory unit further includes a second second-electrode over the resistance variable material. The second-second electrode is associated with the first electrode to define a second memory element.

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.

Abstract: A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The stabilizing solution comprises a non-volatile component, such as non-volatile particles or polymers, which is applied after the photoresist material has been developed. By treating the photoresist with the solution containing a non-volatile component after developing but before drying, the non-volatile component fills the space between adjacent resist patterns and remains on the substrate during drying. The non-volatile component provides structural and mechanical support for the resist to prevent deformation or collapse by liquid surface tension forces.

Abstract: A memory element having a resistance variable material and methods for forming the same are provided. The method includes forming a plurality of first electrodes over a substrate and forming a blanket material stack over the first electrodes. The stack includes a plurality of layers, at least one layer of the stack includes a resistance variable material. The method also includes forming a first conductive layer on the stack and etching the conductive layer and at least one of the layers of the stack to form a first pattern of material stacks. The etched first conductive layer forming a plurality of second electrodes with a portion of the resistance variable material located between each of the first and second electrodes.

Abstract: A method of erasing a chalcogenide variable resistance memory cell is provided. The chalcogenide variable resistance memory cell includes a p-doped substrate with an n-well and a chalcogenide variable resistance memory element. The method includes the step of applying to the variable resistance memory element a voltage that is less than a fixed voltage of the substrate. The applied voltage induces an erase current to flow from the p-doped substrate through the n-well and through the variable resistance memory element.

Abstract: An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.

Abstract: A method of erasing a chalcogenide variable resistance memory cell is provided. The chalcogenide variable resistance memory cell includes a p-doped substrate with an n-well and a chalcogenide variable resistance memory element. The method includes the step of applying to the variable resistance memory element a voltage that is less than a fixed voltage of the substrate. The applied voltage induces an erase current to flow from the p-doped substrate through the n-well and through the variable resistance memory element.

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.

Abstract: A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode, a resistance variable material over the first electrode, and a first second-electrode over the resistance variable material. The first second-electrode is associated with the first electrode to define a first memory element. Each memory unit further includes a second second-electrode over the resistance variable material. The second-second electrode is associated with the first electrode to define a second memory element.

Abstract: A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive material layer. An electrically isolating material layer is formed between the phase change material layer and the energy conversion layer.