Abstract: A pattern data processor system is disclosed that comprises a pattern storage device for storing pattern data, a Redundant Array of Independent Disks (RAID) pattern memory buffer for receiving and temporarily holding the pattern data from the pattern storage device, a shape processor for processing and decoding the pattern data, a shape divider, and a shape generator for generating a shape from the decoded pattern data. The shape processor comprises a programmable gate array device (FPGA) that dynamically decodes different pattern data formats with different decoding schemes, allowing for high speed processing. A Previous Output Shape (POS) Register is also disclosed, which uses information from previous shapes to decompress new shapes, thus allowing for variable length macro and pattern data, and conserving disk space.