Abstract: Techniques for performing user-configurable traffic management functions on streams of packets. The functions include multicasting, discard, scheduling, including shaping, and segmentation and reassembly. In the techniques, the functions are not performed directly on the packets of the stream, but instead on descriptors that represent stored packets. Output of descriptors from all traffic queues, including discard traffic queues, is scheduled. Scheduling is done using a hierarchy of schedulers. The form of the hierarchy and the scheduling algorithms used by the schedulers in the hierarchy are both user configurable. As disclosed, the techniques are implemented in a traffic management coprocessor integrated circuit. The traffic manager coprocessor is used with a digital communications processor integrated circuit that performs switching functions. The buffers for the packets are in the digital communications processor.

Abstract: Techniques for performing user-configurable traffic management functions on streams of packets. The functions include multicasting, discard, scheduling, including shaping, and segmentation and reassembly. In the techniques, the functions are not performed directly on the packets of the stream, but instead on descriptors that represent stored packets. A packet's descriptor includes at least an identifier for the packet and a specifier for a set of traffic management functions to be performed on the descriptor. The user configures a set of traffic management functions for a traffic queue of descriptors. The specifier in the descriptor specifies a set of traffic management functions by specifying a descriptor queue. In multicasting, a descriptor is copied and placed on more than one traffic queue; with regard to discard, when the discard function associated with a traffic queue determines that a packet is to be discarded, the descriptor is placed in a discard traffic queue.

Abstract: Techniques for performing user-configurable traffic management functions on streams of packets. The functions include multicasting, discard, scheduling, including shaping, and segmentation and reassembly. In the techniques, the functions are not performed directly on the packets of the stream, but instead on descriptors that represent stored packets. A packet's descriptor includes at least an identifier for the packet and a specifier for a set of traffic management functions to be performed on the descriptor. The user configures a set of traffic management functions for a traffic queue of descriptors. The specifier in the descriptor specifies a set of traffic management functions by specifying a descriptor queue. In multicasting, a descriptor is copied and placed on more than one traffic queue; with regard to discard, when the discard function associated with a traffic queue determines that a packet is to be discarded, the descriptor is placed in a discard traffic queue.

Abstract: An output skew detection circuit detects and measures output skew tOSLH, tOSHL between multiple in phase common edge output signals propagated through a multiple signal driver circuit having n outputs. The output skew detection circuit senses common edge output skew across the n in phase output signals simultaneously and directly. A first logic gate has n inputs coupled to the n outputs, detects occurrence of either the first or last of the multiple common edge output signals, and generates a first skew detection edge signal at a first logic gate output. The first and last common edge output signals are the signals propagated with minimum and maximum propagation times tplhmin, tphlmin and tplhmax, tphlmax. A second logic gate has n inputs coupled to the n outputs in parallel with the first logic gate. The second logic gate detects occurrence of the other of the first and last of the multiple common edge output signals and generates a second skew detection edge signal at a second logic gate output.

Abstract: A synchronous counter flip flop circuit (20) incorporates a logical AND input circuit (22) having multiple inputs (24) and a first output (25) delivering a first count signal upon concurrence of count logic signals at count logic signal inputs (BIT0-BIT7) with a count enable clock signal at a count enable clock signal input (CET). A count delay circuit (30) is coupled to the first output (25) to provide a second output (32) in parallel with the first output (25) for delivering a delayed second count signal. A logical AND intermediate circuit coupling (34) having first and second inputs coupled respectively to the first and second outputs (25,32) provides a third output (35) delivering a third count signal which is a filtered intermediate terminal count signal (TC). An inverting output buffer circuit (26) provides a final inverted filtered terminal count signal (TC) at the final terminal count output (28).