Abstract: The multiplexing character processor of the present invention multiplexes data characters to and from a plurality of communication lines to a Central Processing Unit by bit slicing. Input data present on the plurality of communication lines is sampled at a rate which is at least 16 times the data bit rate and is formulated as a serial data bit stream. Each sample corresponds to a time slice which slice is allocated to a given communication line under the control of a scan list. A high data rate communication line can be placed on the scan list more than once to insure accurate data reproduction. Character assembly and disassembly is performed in an arithmetic logic unit (ALU) under program control, to provide the flexibility to support various communication link protocols. The input data on each communication line may have a different protocol. Synchronization of the serial data bits to the communication lines is performed by a data bit synchronizer DBS.

Abstract: A data bit synchronizer particularly adapted for use with a multiplexing character processor of the type that multiplexes data characters to and from a plurality of communication lines to a central processing unit. The data bit synchronizer is operable with communication lines carrying various protocols and data bit rates. A RAM memory stores the control and status information for each of the plurality of communication lines.The RAM is accessed at a rate corresponding to the rate used to multiplex the communication lines to repeatedly output the information associated with each communication line. The data bit synchronizer also incorporates a bit rate clock generator for generating timing signals corresponding to selectable output data rates. A multiplexer is used to multiplex the timing signals with the control and status information.