Abstract: A holster which obscures presence and identity of the handgun held by the holster is disclosed. The holster comprises an L-shaped frame having a pin. The handgun is installed on the holster by inserting the pin into the barrel of the handgun. The L-shaped frame combined with the installed handgun collectively form a parallelepiped of thickness equal to that of the handgun. The handgun is disguised by visually meshing in complementary fashion with the holster, when concealed beneath a fabric of an article of apparel.

Abstract: A holster which obscures presence and identity of the handgun held by the holster is disclosed. The holster comprises an L-shaped frame having a pin. The handgun is installed on the holster by inserting the pin into the barrel of the handgun. The L-shaped frame combined with the installed handgun collectively form a parallelepiped of thickness equal to that of the handgun. The handgun is disguised by visually meshing in complementary fashion with the holster, when concealed beneath a fabric of an article of apparel.

Abstract: A holster which obscures presence and identity of the handgun held by the holster is disclosed. The holster comprises an L-shaped frame having a pin. The handgun is installed on the holster by inserting the pin into the barrel of the handgun. The L-shaped frame combined with the installed handgun collectively form a parallelepiped of thickness equal to that of the handgun. The handgun is disguised by visually meshing in complementary fashion with the holster, when concealed beneath a fabric of an article of apparel.

Abstract: A wafer is characterized in that the wafer has a non-uniform distribution of crystal lattice vacancies, wherein the concentration of crystal lattice vacancies in the bulk layer are greater than the concentration of crystal lattice vacancies in the front surface layer. In addition, the front surface of the wafer has an epitaxial layer, having a thickness of less than about 2.0 çm, deposited thereon. A process comprises heating a surface of a wafer starting material to remove a silicon oxide layer from the surface and depositing an epitaxial layer onto the surface to form an epitaxial wafer. The epitaxial wafer is then heated to a soak temperature of at least about 1175C. while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant, and the wafer is cooled at a rate of at least about 10C./sec.

Abstract: A wafer is characterized in that the wafer has a non-uniform distribution of crystal lattice vacancies, wherein the concentration of crystal lattice vacancies in the bulk layer are greater than the concentration of crystal lattice vacancies in the front surface layer. In addition, the front surface of the wafer has an epitaxial layer, having a thickness of less than about 2.0 ?m, deposited thereon. A process comprises heating a surface of a wafer starting material to remove a silicon oxide layer from the surface and depositing an epitaxial layer onto the surface to form an epitaxial wafer. The epitaxial wafer is then heated to a soak temperature of at least about 1175° C. while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant, and the wafer is cooled at a rate of at least about 10° C./sec.

Abstract: This invention is directed to a novel a single crystal silicon wafer. In one embodiment, this wafer comprises: (a) two major generally parallel surfaces (i.e., the front and back surfaces); (b) a central plane between and parallel to the front and back surfaces; (c) a front surface layer which comprises the region of the wafer extending a distance of at least about 10 &mgr;m from the front surface toward the central plane; and (d) a bulk layer which comprises the region of the wafer extending from the central plane to the front surface layer.

Abstract: A process for manufacturing a semiconductor wafer comprises first etching the wafer to reduce damage on the front and back surfaces. An epitaxial layer is grown on the etched front surface of the semiconductor wafer to improve the surface roughness of the front surface. Finally, the front surface of the wafer is final polished to further improve the surface roughness of the front surface.

Abstract: This invention is directed to a novel a single crystal silicon wafer. In one embodiment, this wafer comprises: (a) two major generally parallel surfaces (i.e., the front and back surfaces); (b) a central plane between and parallel to the front and back surfaces; (c) a front surface layer which comprises the region of the wafer extending a distance of at least about 10 &mgr;m from the front surface toward the central plane; and (d) a bulk layer which comprises the region of the wafer extending from the central plane to the front surface layer.

Abstract: This invention is directed to a novel a single crystal silicon wafer. The wafer comprises: (a) two major generally parallel surfaces (ie., the front and back surfaces); (b) a central plane between and parallel to the front and back surfaces; (c) a front surface layer which comprises the region of the wafer extending a distance of at least about 10 &mgr;m from the front surface toward the central plane; and (d) a bulk layer which comprises the region of the wafer extending from the central plane to the front surface layer.

Abstract: A horizontal reactor for depositing an epitaxial layer on a semiconductor wafer. The reactor includes a reaction chamber sized and shaped for receiving the semiconductor wafer and a susceptor having an outer edge and a generally planar wafer receiving surface positioned in the reaction chamber for supporting the semiconductor wafer. In addition, the reactor includes a heating array positioned outside the reaction chamber including a plurality of heat lamps and a primary reflector for directing thermal radiation emitted by the heat lamps toward the susceptor to heat the semiconductor wafer and susceptor. Further, the reactor includes a secondary edge reflector having a specular surface positioned beside the heating array for recovering misdirected thermal radiation directed generally to a side of the heating array and away from the susceptor.

Abstract: N+ type semiconductor substrates containing oxygen are thermally treated to enhance internal gettering capabilities by heating at 1050.degree. to 1200.degree. C., then at 500.degree. to 900.degree. C. and finally at 950.degree. to 1250.degree. C.