Patents by Inventor Jon T. Fitch
Jon T. Fitch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11989041Abstract: In one embodiment, a method for decreasing a humidity level in an information handling system includes: receiving, by a sound field chamber, an incoming airflow, the incoming airflow having a humidity level corresponding to an amount of water vapor in the incoming airflow; identifying, by a humidity controller, the humidity level of the incoming airflow; determining, by the humidity controller, that the humidity level is greater than a threshold humidity level; and in response to determining that the humidity level is greater than the threshold humidity level: causing, by the humidity controller, a sound source of the information handling system to generate a sound field within the sound field chamber, the sound field comprised of sound waves, the sound waves causing an acoustic agglomeration of the water vapor, the acoustic agglomeration causing the humidity level to decrease.Type: GrantFiled: January 11, 2022Date of Patent: May 21, 2024Assignee: Dell Products L.P.Inventors: Chris E. Peterson, Sandor Farkas, Steven T. Embleton, Jon T. Fitch
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Publication number: 20230221738Abstract: In one embodiment, a method for decreasing a humidity level in an information handling system includes: receiving, by a sound field chamber, an incoming airflow, the incoming airflow having a humidity level corresponding to an amount of water vapor in the incoming airflow; identifying, by a humidity controller, the humidity level of the incoming airflow; determining, by the humidity controller, that the humidity level is greater than a threshold humidity level; and in response to determining that the humidity level is greater than the threshold humidity level: causing, by the humidity controller, a sound source of the information handling system to generate a sound field within the sound field chamber, the sound field comprised of sound waves, the sound waves causing an acoustic agglomeration of the water vapor, the acoustic agglomeration causing the humidity level to decrease.Type: ApplicationFiled: January 11, 2022Publication date: July 13, 2023Inventors: Chris E. Peterson, Sandor Farkas, Steven T. Embleton, Jon T. Fitch
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Patent number: 11579074Abstract: An information handling system includes a corrosion controller that may monitor a corrosion sensor array, and determine a type of the corrosion based on a location of a corrosion sensor. The corrosion type may include humidity driven corrosion and non-humidity driven corrosion.Type: GrantFiled: March 5, 2021Date of Patent: February 14, 2023Assignee: Dell Products L.P.Inventors: Jon T. Fitch, Steven Embleton, Sandor Farkas, Danny King
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Publication number: 20220326747Abstract: In one embodiment, a method for reducing corrosion in an information handling system includes receiving a system setting indicating one or more operation modes; identifying an ambient temperature of the information handling system, the ambient temperature captured by one or more sensors of the information handling system; identifying a humidity level of the information handling system, the humidity level captured by the one or more sensors; identifying a corrosion risk value based on the ambient temperature and the humidity level; determining that the corrosion risk value is greater than a threshold corrosion risk value; and in response to determining that the corrosion risk value is greater than the threshold corrosion risk value: modifying one or more device threshold settings based on the system setting and the corrosion risk value, wherein modifying the one or more device threshold settings causes the ambient temperature to increase and the humidity level to decrease.Type: ApplicationFiled: April 9, 2021Publication date: October 13, 2022Inventors: Jon T. Fitch, Sandor T. Farkas, Joseph D. King, Steven T. Embleton
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Publication number: 20220283079Abstract: An information handling system includes a corrosion controller that may monitor a corrosion sensor array, and determine a type of the corrosion based on a location of a corrosion sensor. The corrosion type may include humidity driven corrosion and non-humidity driven corrosion.Type: ApplicationFiled: March 5, 2021Publication date: September 8, 2022Inventors: Jon T. Fitch, Steven Embleton, Sandor Farkas, Danny King
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Patent number: 5627395Abstract: A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.Type: GrantFiled: November 2, 1995Date of Patent: May 6, 1997Assignee: Motorola Inc.Inventors: Keith E. Witek, Jon T. Fitch, Carlos A. Mazure
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Patent number: 5612563Abstract: A transistor (10) has a substrate (12) and a diffusion (14). A gate conductive layer (18) overlies the substrate (12) and has a sidewall formed by an opening that exposes the substrate (12). A sidewall dielectric layer (22) formed laterally adjacent the conductive layer (18) sidewall functions as a gate dielectric for the transistor (10). A conductive region is formed within the opening. The conductive region has a first current electrode region (28) and a second control electrode region (34) and a channel region (30) laterally adjacent the sidewall dielectric layer (22). A plurality of transistors, each in accordance with transistor (10), can be stacked in a vertical manner to form logic gates such as NMOS or PMOS NAND, NOR, and inverter gates, and/or CMOS NAND, NOR, and inverter gates with one or more inputs.Type: GrantFiled: January 25, 1994Date of Patent: March 18, 1997Assignee: Motorola Inc.Inventors: Jon T. Fitch, Carlos A. Mazure, Keith E. Witek
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Patent number: 5578850Abstract: A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34).Type: GrantFiled: January 16, 1996Date of Patent: November 26, 1996Assignee: Motorola Inc.Inventors: Jon T. Fitch, Carlos A. Mazure, Keith E. Witek
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Patent number: 5554870Abstract: An integrated circuit (10) has a vertical device, such as a transistor (71), formed by epitaxial growth from a substrate (12) and a horizontal device, such as a transistor (73, 75) grown epitaxially from the vertical device. In accordance with one embodiment of the invention, all six transistors of an SRAM cell can be formed in single crystal material for improved device characteristics and increased cell density. Utilization of various combinations of vertical and horizontal devices permits a large degree of vertical integration within semiconductor devices.Type: GrantFiled: August 2, 1995Date of Patent: September 10, 1996Assignee: Motorola, Inc.Inventors: Jon T. Fitch, Suresh Venkatesan, Keith E. Witek
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Patent number: 5527723Abstract: A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.Type: GrantFiled: October 3, 1994Date of Patent: June 18, 1996Assignee: Motorola, Inc.Inventors: Keith E. Witek, Jon T. Fitch, Carlos A. Mazure
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Patent number: 5510645Abstract: A method for forming an air region or an air bridge overlying a base layer (12). Air regions (20a, 20b, 28a, and 48) are formed overlying the base layer (12) to provide for improved dielectric isolation of adjacent conductive layers, provide air-isolated conductive interconnects, and/or form many other microstructures or microdevices. The air regions (20a, 20b, 28a, and 48) are formed by either selectively removing a sacrificial spacer (16a and 16b) or by selectively removing a sacrificial layer (28, 40). The air regions (20a, 20b, 28a, and 48) are sealed, enclosed, or isolated by either a selective growth process or by a non-conformal deposition technique. The air regions (20a, 20b, 28a, and 48) may be formed under any pressure, gas concentration, or processing condition (i.e. temperature, etc.). The air regions (20a, 20b, 28a, and 48) may be formed at any level within an integrated circuit.Type: GrantFiled: January 17, 1995Date of Patent: April 23, 1996Assignee: Motorola, Inc.Inventors: Jon T. Fitch, Papu Maniar, Keith E. Witek, Jerry Gelatos, Reza Moazzami, Sergio A. Ajuria
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Patent number: 5451538Abstract: A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34). A capacitor (69) is formed overlying and coupled to the vertical transistor (10) in order to form a dynamic random access memory (DRAM) cell.Type: GrantFiled: April 20, 1994Date of Patent: September 19, 1995Assignee: Motorola, Inc.Inventors: Jon T. Fitch, Carlos A. Mazure, Keith E. Witek
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Patent number: 5414289Abstract: A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34).Type: GrantFiled: November 9, 1993Date of Patent: May 9, 1995Assignee: Motorola, Inc.Inventors: Jon T. Fitch, Carlos A. Mazure, Keith E. Witek
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Patent number: 5414288Abstract: A method for forming a vertical transistor (10) begins by providing a substrate (12). A conductive layer (16) is formed overlying the substrate (12). A first current electrode (26), a second current electrode (30), and a channel region (28) are each formed via one of either selective growth, epitaxial growth, in-situ doping, and/or ion implantation. A gate electrode or control electrode (34) is formed laterally adjacent the channel region (28). A selective/epitaxial growth step is used to connect the conductive layer (16) to the control electrode (34) and forms a control electrode interconnect which is reliable and free from electrical short circuits to the current electrodes (26 and 30). The transistor (10) may be vertically stacked to form compact inverter circuits.Type: GrantFiled: February 16, 1994Date of Patent: May 9, 1995Assignee: Motorola, Inc.Inventors: Jon T. Fitch, Carlos A. Mazure, Keith E. Witek
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Patent number: 5398200Abstract: A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.Type: GrantFiled: January 18, 1994Date of Patent: March 14, 1995Assignee: Motorola, Inc.Inventors: Carlos A. Mazure, Jon T. Fitch, James D. Hayden, Keith E. Witek
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Patent number: 5393681Abstract: A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.Type: GrantFiled: March 15, 1994Date of Patent: February 28, 1995Assignee: Motorola, Inc.Inventors: Keith E. Witek, Jon T. Fitch, Carlos A. Mazure
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Patent number: 5376562Abstract: A transistor is formed as either a bipolar transistor (10) or an MOS transistor (11). Each transistor (10 or 11) has a substrate (12). Bipolar transistor (10) has a first current electrode (26) underlying a control electrode (28), and a second current electrode (32) overlying the control electrode (28). MOS transistor (11) has a first current electrode (54) underlying a channel region (56), and a source lightly doped region (58) and a source heavily doped region (60) overlying the channel region (56). A control electrode conductive layer (40) is laterally adjacent a sidewall dielectric layer (48), and sidewall dielectric layer (48) is laterally adjacent channel region (56). Conductive layer (40) functions as a gate electrode for transistor (11). Each of the transistors (10 and 11) is vertically integrated such as in a vertically integrated BiMOS circuit. Transistors (10 and 11) can be electrically isolated by isolation ( 64 and 66).Type: GrantFiled: May 24, 1993Date of Patent: December 27, 1994Assignee: Motorola, Inc.Inventors: Jon T. Fitch, Carlos A. Mazure, Keith E. Witek, James D. Hayden
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Method for forming a transistor having a dynamic connection between a substrate and a channel region
Patent number: 5340754Abstract: A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.Type: GrantFiled: September 2, 1992Date of Patent: August 23, 1994Assignee: Motorla, Inc.Inventors: Keith E. Witek, Jon T. Fitch, Carlos A. Mazure -
Patent number: 5324673Abstract: A method for forming a vertical transistor (10) begins by providing a substrate (12). A conductive layer (16) is formed overlying the substrate (12). A first current electrode (26), a second current electrode (30), and a channel region (28) are each formed via one of either selective growth, epitaxial growth, in-situ doping, and/or ion implantation. A gate electrode or control electrode (34) is formed laterally adjacent the channel region (28). A selective/epitaxial growth step is used to connect the conductive layer (16) to the control electrode (34) and forms a control electrode interconnect which is reliable and free from electrical short circuits to the current electrodes (26 and 30). The transistor (10) may be vertically stacked to form compact inverter circuits.Type: GrantFiled: November 19, 1992Date of Patent: June 28, 1994Assignee: Motorola, Inc.Inventors: Jon T. Fitch, Carlos A. Mazure, Keith E. Witek
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Patent number: 5324683Abstract: A method for forming an air region or an air bridge overlying a base layer (12). Air regions (20a, 20b, 28a, and 48) are formed overlying the base layer (12) to provide for improved dielectric isolation of adjacent conductive layers, provide air-isolated conductive interconnects, and/or form many other microstructures or microdevices. The air regions (20a, 20b, 28a, and 48) are formed by either selectively removing a sacrificial spacer (16a and 16b) or by selectively removing a sacrificial layer (28, 40). The air regions (20a, 20b, 28a, and 48) are sealed, enclosed, or isolated by either a selective growth process or by a non-conformal deposition technique. The air regions (20a, 20b, 28a, and 48) may be formed under any pressure, gas concentration, or processing condition (i.e. temperature, etc.). The air regions (20a, 20b, 28a, and 48) may be formed at any level within an integrated circuit.Type: GrantFiled: June 2, 1993Date of Patent: June 28, 1994Assignee: Motorola, Inc.Inventors: Jon T. Fitch, Papu Maniar, Keith E. Witek, Jerry Gelatos, Reza Moazzami, Sergio A. Ajuria