Abstract: A method for graph processing in a scalable graph processing framework may include applying a two-dimensional partitioning scheme to partition a graph. One or more partitions of the graph may be distributed to each graph core such that each graph core executes a graph processing algorithm on one or more partitions of the graph. The executing of the graph processing algorithm may include the graph cores exchanging vertex labels via a crossbar interconnecting the plurality of graph cores. Each graph core in the scalable graph processing framework may be coupled with a single memory channel upon which the partitions of the graph are distributed. The graph cores may synthesized on a field programmable gate array (FPGA) based on one or more user defined functions (UDFs). Related systems and computer program products are also provided.

Abstract: A method may include parsing, using a JavaScript Object Notation (JSON) parser implemented on a field programmable gate array (FPGA), a JSON document. The parsing includes dividing an input string comprising the JSON document into one or more data blocks and annotating the characters included in each data block a bitmap for each data block. String characters included in the data blocks may be identified, based on the bitmap associated with each data block, for writing to a string array. Numeric characters included in the data blocks may be transformed, based on the bitmap associated with each data block, into integers value for writing to an integer array or float values for writing to a float array. A tape including a binary representation of the JSON document may be generated based on the bitmap associated with each data block. Related systems and computer program products are also provided.

Abstract: A method for graph processing in a scalable graph processing framework may include applying a two-dimensional partitioning scheme to partition a graph. One or more partitions of the graph may be distributed to each graph core such that each graph core executes a graph processing algorithm on one or more partitions of the graph. The executing of the graph processing algorithm may include the graph cores exchanging vertex labels via a crossbar interconnecting the plurality of graph cores. Each graph core in the scalable graph processing framework may be coupled with a single memory channel upon which the partitions of the graph are distributed. The graph cores may synthesized on a field programmable gate array (FPGA) based on one or more user defined functions (UDFs). Related systems and computer program products are also provided.

Abstract: Methods, systems, and computer-readable storage media for providing a simulated graph processing accelerator representative of a hardware-based graph processing accelerator, the simulated graph processing accelerator including a controller component, a set of producer components, and a final merge component; triggering execution of the simulated graph processing accelerator as a simulation of processing of a graph for one or more of breadth-first search (BFS), single source shortest path (SSSP), weakly connected components (WCC), sparse matrix-vector multiplication (SpMV), and PageRank (PR), execution including: generating request streams from each producer component, merging request streams to provide a merged request stream, inputting the merged request stream to a memory simulator, and processing, by the memory simulator, the merged request stream to simulate handling of requests in memory.

Abstract: Example embodiments of the present disclosure include an integration system comprising a machine-readable medium (e.g., a memory) and a reconfigurable logic device (e.g., an FPGA). The machine-readable medium stores configuration data that configures the reconfigurable logic device to include a first channel adapter, a first message processor, a second message processor, a message channel, and a second channel adapter. The first channel adapter is configured to receive input data written by a first message endpoint. The first message processor is configured to perform a first message processing operation on messages received from the first channel adapter that include the input data. The second message processor is configured to perform a second message processing operation on messages received from the first message processor. The message channel facilitates communication between the first and second message processors.

Abstract: Example embodiments of the present disclosure include an integration system comprising a machine-readable medium (e.g., a memory) and a reconfigurable logic device (e.g., an FPGA). The machine-readable medium stores configuration data that configures the reconfigurable logic device to include a first channel adapter, a first message processor, a second message processor, a message channel, and a second channel adapter. The first channel adapter is configured to receive input data written by a first message endpoint. The first message processor is configured to perform a first message processing operation on messages received from the first channel adapter that include the input data. The second message processor is configured to perform a second message processing operation on messages received from the first message processor. The message channel facilitates communication between the first and second message processors.