Abstract: A system is described. The system includes a control transistor, a voltage source, a feedback node connected between a drain of the control transistor and the voltage source, a plurality of resistors connected between the voltage source and ground, and a control node connected to a gate of the control transistor. The resistors include a first series-connected set of resistors associated with the control transistor being biased and a second series-connected set of resistors associated with the control transistor being unbiased. During a startup period, the control node is configured to bias the control transistor to select the first series-connected set of resistors, thereby increasing a voltage level of the voltage source to a boosted VCC voltage. After the startup period, the control node is configured to unbias the control transistor to select the second series-connected set of resistors, thereby decreasing the boosted VCC voltage to a normal VCC voltage.

Abstract: A device comprises a processor, a memory for storing instruction code that is executable by the processor, and power supply circuitry. The power supply circuitry is in communication with the processor. The power supply circuitry comprises voltage regulator circuitry, a capacitor, a current limiter, and a switch. The voltage regulator circuitry comprises an input electrically coupled to a voltage source and an output configured to provide a regulated voltage output. The capacitor is configured to store energy derived from the voltage source. The capacitor comprises a first node electrically coupled with the output of the voltage regulator circuitry. The current limiter is in electrical communication with a second node of the capacitor and configured to limit inrush current through the capacitor during a start-up phase of the power supply circuitry. The switch circuit is in electrical communication with the second node of the capacitor.

Abstract: A includes a plurality of power supply units, a processor, and a non-transitory computer readable medium having instructions stored thereon that, when engaged by the processor, cause performance of a set of functions. The set of functions includes detecting an overcurrent of a first power supply unit of the plurality of power supply units. The set of functions includes determining that the overcurrent of the first power supply unit corresponds to current sharing between the plurality of power supply units. The set of functions includes in response to determining that the overcurrent of the first power supply corresponds to the current sharing, suppressing an overcurrent protection mode of the first power supply.

Abstract: A system is described. The system includes a control transistor, a voltage source, a feedback node connected between a drain of the control transistor and the voltage source, a plurality of resistors connected between the voltage source and ground, and a control node connected to a gate of the control transistor. The resistors include a first series-connected set of resistors associated with the control transistor being biased and a second series-connected set of resistors associated with the control transistor being unbiased. During a startup period, the control node is configured to bias the control transistor to select the first series-connected set of resistors, thereby increasing a voltage level of the voltage source to a boosted VCC voltage. After the startup period, the control node is configured to unbias the control transistor to select the second series-connected set of resistors, thereby decreasing the boosted VCC voltage to a normal VCC voltage.