Abstract: A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.

Abstract: A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.

Abstract: A stackable memory system for minimizing the stub lengths of the memory data bus and data skew. The invention provides a memory controller, a memory connector, a data bus, a first stackable memory module and a terminator plate. The data bus electrically connects the controller to the memory connector. The first stackable memory module is mechanically and electrically connected to the memory connector. The terminator plate is adapted to substantially reduce reflections to the data bus and is electrically connected to the data bus through the first stackable memory module. Additional, the memory system may be expanded by adding stackable memory modules substantially similar to the first stackable memory module to the stackable memory system between the first memory module and the terminator plate. Each stackable memory module may include memory chips each of which has trace lines connecting the memory chip to a module connector.