Patents by Inventor Jonathan Doebler
Jonathan Doebler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9337053Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.Type: GrantFiled: November 12, 2012Date of Patent: May 10, 2016Assignee: Micron Technology, Inc.Inventor: Jonathan Doebler
-
Patent number: 9147473Abstract: Apparatuses, global and local wordline drivers, and methods for driving a wordline voltage in a memory is described. An example apparatus includes a memory array including a plurality of sub-arrays. The plurality of sub arrays are coupled to a wordline. The memory array further including a plurality of local wordline drivers coupled between a global wordline and the wordline. The plurality of local wordline drivers are configured to selectively couple the wordline to the global wordline during a memory access operation. The example apparatus further includes a global wordline driver configured to selectively couple the wordline to the global wordline during the memory access operation.Type: GrantFiled: August 1, 2013Date of Patent: September 29, 2015Assignee: Micron Technology, Inc.Inventors: Tae Kim, Howard Kirsch, Charles Ingalls, K. Shawn Smith, Jonathan Doebler
-
Patent number: 9006911Abstract: A method for forming patterns of dense conductor lines and their contact pads is described. Parallel base line patterns are formed over a substrate. Each of the base line patterns is trimmed. Derivative line patterns and derivative transverse patterns are formed as spaces on the sidewalls of the trimmed base line patterns, wherein the derivative transverse patterns are formed between the ends of the derivative line patterns and adjacent to the ends of the trimmed base line patterns. The trimmed base line patterns are removed. At least end portions of the derivative line patterns are removed, such that the derivative line patterns are separated from each other and all or portions of the derivative transverse patterns become patterns of contact pads each connected with a derivative line pattern.Type: GrantFiled: May 16, 2012Date of Patent: April 14, 2015Assignee: Nanya Technology CorporationInventors: Jonathan Doebler, Scott Sills
-
Publication number: 20150036442Abstract: Apparatuses, global and local wordline drivers, and methods for driving a wordline voltage in a memory is described. An example apparatus includes a memory array including a plurality of sub-arrays. The plurality of sub arrays are coupled to a wordline. The memory array further including a plurality of local wordline drivers coupled between a global wordline and the wordline. The plurality of local wordline drivers are configured to selectively couple the wordline to the global wordline during a memory access operation. The example apparatus further includes a global wordline driver configured to selectively couple the wordline to the global wordline during the memory access operation.Type: ApplicationFiled: August 1, 2013Publication date: February 5, 2015Applicant: Micron Technology, Inc.Inventors: Tae Kim, Howard Kirsch, Charles Ingalls, K. Shawn Smith, Jonathan Doebler
-
Patent number: 8884351Abstract: Devices having hybrid-vertical contacts. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.Type: GrantFiled: February 26, 2013Date of Patent: November 11, 2014Assignee: Micron Technology, Inc.Inventor: Jonathan Doebler
-
Publication number: 20130307166Abstract: A method for forming patterns of dense conductor lines and their contact pads is described. Parallel base line patterns are formed over a substrate. Each of the base line patterns is trimmed. Derivative line patterns and derivative transverse patterns are formed as spaces on the sidewalls of the trimmed base line patterns, wherein the derivative transverse patterns are formed between the ends of the derivative line patterns and adjacent to the ends of the trimmed base line patterns. The trimmed base line patterns are removed. At least end portions of the derivative line patterns are removed, such that the derivative line patterns are separated from each other and all or portions of the derivative transverse patterns become patterns of contact pads each connected with a derivative line pattern.Type: ApplicationFiled: May 16, 2012Publication date: November 21, 2013Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Jonathan Doebler, Scott Sills
-
Patent number: 8389373Abstract: Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.Type: GrantFiled: December 16, 2010Date of Patent: March 5, 2013Assignee: Micron Technology, Inc.Inventor: Jonathan Doebler
-
Patent number: 8329534Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.Type: GrantFiled: September 28, 2010Date of Patent: December 11, 2012Assignee: Micron Technology, Inc.Inventor: Jonathan Doebler
-
Publication number: 20110086489Abstract: Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.Type: ApplicationFiled: December 16, 2010Publication date: April 14, 2011Applicant: Micron Technology, Inc.Inventor: Jonathan Doebler
-
Publication number: 20110014787Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.Type: ApplicationFiled: September 28, 2010Publication date: January 20, 2011Applicant: MICRON TECHNOLOGY, INC.Inventor: Jonathan Doebler
-
Patent number: 7863663Abstract: Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.Type: GrantFiled: April 7, 2006Date of Patent: January 4, 2011Assignee: Micron Technology, Inc.Inventor: Jonathan Doebler
-
Patent number: 7807582Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.Type: GrantFiled: March 6, 2006Date of Patent: October 5, 2010Assignee: Micron Technology, Inc.Inventor: Jonathan Doebler
-
Publication number: 20070235789Abstract: Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.Type: ApplicationFiled: April 7, 2006Publication date: October 11, 2007Inventor: Jonathan Doebler
-
Publication number: 20070207620Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.Type: ApplicationFiled: March 6, 2006Publication date: September 6, 2007Inventor: Jonathan Doebler