Abstract: A system comprises a processor, a reassembly buffer that receives mini-packets, and at least one data structure that comprises bits. The bits indicate the presence or absence of each of the mini-packets in the reassembly buffer and further indicate whether one of the mini-packets is a final mini-packet in a series of the mini-packets. The processor uses the bits to determine whether all mini-packets forming the series are present in the reassembly buffer. As a result of the determination, the processor causes the series to be read from the reassembly buffer.

Abstract: A method for mitigating detected patterns in a network device is described herein. A packet is moved through a first pipeline of the network device, to perform processing of the packet. A pattern is detected within the packet. In response to detecting the pattern, a hardware component of the network device generates a flag as the packet is moving through the first pipeline, in parallel with the processing of the packet. One or more forwarding policies associated with the packet are determined using the flag.

Abstract: An apparatus and method of protecting against a denial-of-service (DoS) attack are described. The apparatus comprises a classification engine, a meter engine, and a copy engine. The method comprises assigning a received packet to a meter based upon a classification of the network packet, determining that a DoS attack is in progress based upon a meter count, copying at least one packet from the meter to a processor; and suppressing the copying of subsequently received network packets to the processor.

Abstract: Techniques described herein provide for sending request messages. The request messages may be sent in order. The request messages may be sent over a designated communications channel.

Abstract: A method of providing redundancy in a ternary content addressable memory (TCAM), the method including detecting a defective entry in building block in a ternary content addressable memory (TCAM), configuring a failover logic to redirect a software query toward a spare building block and away from the building block with the defective entry, and avoiding in using the building block with the defective entry.

Abstract: A system comprises a processor, a reassembly buffer that receives mini-packets, and at least one data structure that comprises bits. The bits indicate the presence or absence of each of the mini-packets in the reassembly buffer and further indicate whether one of the mini-packets is a final mini-packet in a series of the mini-packets. The processor uses the bits to determine whether all mini-packets forming the series are present in the reassembly buffer. As a result of the determination, the processor causes the series to be read from the reassembly buffer.

Abstract: One embodiment relates to a method of generating an N-bit checksum for variable-length data. An N-bit data word of the variable-length data is received by data input circuitry, and an N-bit input checksum generator is used to calculate an updated value of the N-bit checksum for N-bit data words. A plurality of smaller checksum generators and the N-bit input checksum generator are each used to calculate a last value of the N-bit checksum for the last data word of the variable-length data. Control signals are used to controllably select the last value of the N-bit checksum from outputs of said checksum generators. Other embodiments and features are also disclosed.

Abstract: A method of providing redundancy in a ternary content addressable memory (TCAM), the method including detecting a defective entry in building block in a ternary content addressable memory (TCAM), configuring a failover logic to redirect a software query toward a spare building block and away from the building block with the defective entry, and avoiding in using the building block with the defective entry.

Abstract: In an embodiment of the invention, a method of providing redundancy in a ternary content addressable memory (TCAM) includes: detecting a defective entry in a ternary content addressable memory (TCAM); marking the defective entry so that the defective entry is visible to a software; and avoiding in using the defective entry. For data that normally would have been written into the defective entry, the data is written into an entry that is subsequent to the defective entry. In another embodiment, the redundancy is provided in a CAM instead of a TCAM.

Abstract: An apparatus and method of protecting against a denial-of-service (DoS) attack are described. The apparatus comprises a classification engine, a meter engine, and a copy engine. The method comprises assigning a received packet to a meter based upon a classification of the network packet, determining that a DoS attack is in progress based upon a meter count, copying at least one packet from the meter to a processor; and suppressing the copying of subsequently received network packets to the processor.

Abstract: One embodiment relates to a method of generating an N-bit checksum for variable-length data. An N-bit data word of the variable-length data is received by data input circuitry, and an N-bit input checksum generator is used to calculate an updated value of the N-bit checksum for N-bit data words. A plurality of smaller checksum generators and the N-bit input checksum generator are each used to calculate a last value of the N-bit checksum for the last data word of the variable-length data. Control signals are used to controllably select the last value of the N-bit checksum from outputs of said checksum generators. Other embodiments and features are also disclosed.

Abstract: A system and method for performing counting operations for a plurality of components is disclosed. A memory stores a plurality of counts from different components. The memory is coupled to a counter and the plurality of counts are accessible to the adder for adding addends to the plurality of counts. A count engine controls the adding of the addends to the plurality of counts.

Abstract: A system and method for performing counting operations for a plurality of components is disclosed. A memory stores a plurality of counts from different components. The memory is coupled to a counter and the plurality of counts are accessible to the adder for adding addends to the plurality of counts. A count engine controls the adding of the addends to the plurality of counts.