Abstract: A golf club head including a striking face, a periphery portion surrounding and extending rearwards from the striking face, a damping element including a front surface and a rear surface, the rear surface of the damping element opposite the front surface of the damping element, wherein the striking face comprises a first portion having a substantially constant thickness, wherein the front surface of the damping element comprises a geometric center, wherein the striking face comprises a second portion, the second portion of the striking face located heelward of the center face plane, the second portion of the striking face having a thickness which tapers from a maximum thickness at a thick end of the second portion to a minimum thickness at a thin end of the second portion, wherein the thick end is located toeward of the thin end.

Abstract: A processor is disclosed including: a barrel-threaded execution unit for executing concurrent threads, and a repeat cache shared between the concurrent threads. The processor's instruction set includes a repeat instruction which takes a repeat count operand. When the repeat cache is not claimed and the repeat instruction is executed in a first thread, a portion of code is cached from the first thread into the repeat cache, the state of the repeat cache is changed to record it as claimed, and the cached code is executed a number of times. When the repeat instruction is then executed in a further thread, then the already-cached portion of code is again executed a respective number of times, each time from the repeat cache. For each of the first and further instructions, the repeat count operand in the respective instruction specifies the number of times to execute the cached code.

Abstract: An improved method and apparatus for performing operations (such as Viterbi decode) in digital processors using a reduced number of cycles. In one aspect, the invention comprises efficient methods for performing multiple “butterfly” add-compare-select (ACS) operations using an improved dual butterfly (DVBF) extension instruction added to the instruction set of a user-configured processor. The DVBF extension allows performance of two butterfly operations in a single cycle. In another aspect, an improved path metric addressing scheme is disclosed. An integrated circuit (IC) device incorporating the aforementioned features, and method of designing such IC, are also disclosed.

Abstract: An improved method and apparatus for performing operations (such as Viterbi decode) in digital processors using a reduced number of cycles. In one aspect, the invention comprises efficient methods for performing multiple “butterfly” add-compare-select (ACS) operations using an improved dual butterfly (DVBF) extension instruction added to the instruction set of a user-configured processor. The DVBF extension allows performance of two butterfly operations in a single cycle. In another aspect, an improved path metric addressing scheme is disclosed. An integrated circuit (IC) device incorporating the aforementioned features, and method of designing such IC, are also disclosed.

Abstract: An improved method and apparatus for performing operations (such as Viterbi decode) in digital processors using a reduced number of cycles. In one aspect, the invention comprises efficient methods for performing multiple “butterfly” add-compare-select (ACS) operations using an improved dual butterfly (DVBF) extension instruction added to the instruction set of a user-configured processor. The DVBF extension allows performance of two butterfly operations in a single cycle. In another aspect, an improved path metric addressing scheme is disclosed. An integrated circuit (IC) device incorporating the aforementioned features, and method of designing such IC, are also disclosed.

Abstract: An improved method and apparatus for performing operations (such as Viterbi decode) in digital processors using a reduced number of cycles. In one aspect, the invention comprises efficient methods for performing multiple “butterfly” add-compare-select (ACS) operations using an improved dual butterfly (DVBF) extension instruction added to the instruction set of a user-configured processor. The DVBF extension allows performance of two butterfly operations in a single cycle. In another aspect, an improved path metric addressing scheme is disclosed. An integrated circuit (IC) device incorporating the aforementioned features, and method of designing such IC, are also disclosed.

Abstract: An improved method and apparatus for performing operations (such as Viterbi decode) in digital processors using a reduced number of cycles. In one aspect, the invention comprises efficient methods for performing multiple “butterfly” add-compare-select (ACS) operations using an improved dual butterfly (DVBF) extension instruction added to the instruction set of a user-configured processor. The DVBF extension allows performance of two butterfly operations in a single cycle. In another aspect, an improved path metric addressing scheme is disclosed. An integrated circuit (IC) device incorporating the aforementioned features, and method of designing such IC, are also disclosed.

Abstract: Computer-implemented method and system for generating an optimized description of an arithmetic function comprising at least two of an addition, a multiplication, and a rounding operation to be carried out on a plurality of data bits in a plurality of registers of an electronic circuit, the method comprising the steps: obtaining a first description of the arithmetic function; decomposing the first description to obtain a second description comprising individual binary and logical operations on data bits, wherein the data bits are arranged to their proper place value, the second description being substantially arithmetically equivalent to the first description; obtaining a third description by parallelizing at least two of the binary and logical operations on the data bits in the second description; providing a forth description comprising operations for each data bit comprised in the third description in a hardware description language as the optimized description of the electronic circuit.

Abstract: Digital processor apparatus having an instruction set architecture (ISA) with instruction words of varying length. In the exemplary embodiment, the processor comprises an extended user-configurable RISC processor with four-stage pipeline (fetch, decode, and writeback) and associated logic that is adapted to decode and process both 32-execute, bit and 16-bit instruction words present in a single program, thereby increasing the flexibility of the instruction set, and allowing for greater code compression and reduced memory overhead. Free-form use of the different length instructions is provided with no required mode shift. An improved instruction aligner and code compression architecture is also disclosed.