Patents by Inventor Jonathan Graf

Jonathan Graf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240308001
    Abstract: An apparatus for additively manufacturing three-dimensional objects may include at least one calibration unit, at least one irradiation device, and a determination device. The least one calibration unit may include at least one calibration region arranged in the beam guiding plane, and the at least one calibration region may include a plurality of sub-regions differing in respect of at least one optical property. The at least one irradiation device may be configured to guide a plurality of energy beams across the at least one calibration region comprising the plurality of sub-regions, and a plurality of calibration signals may be generated by the plurality of sub-regions being irradiated with the plurality of energy beams. The determination device may be configured to determine the plurality of calibration signals and to determine a calibration status of the irradiation device based at least in part on the determined plurality of calibration signals.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Juergen Werner, Dominic Graf, Jonathan William Ortner, Lisa Pastuschka, Tobias Bokkes
  • Publication number: 20230148108
    Abstract: A computer system obtains and/or assists in creation of a natural language description file corresponding to a design, where the design is a hardware design or a software design and processes the natural language description file to extract semantic expressions. One or more intermediate representation data structures is generated from selected ones of the semantic expressions. Each intermediate representation data structure includes natural language design objects, natural language design object properties, and relationships between natural language design objects and/or natural language design object properties. The computer system transforms each intermediate representation data structure into one or more corresponding design verification statements derived from the natural language description file. Those design verification statements are subsequently evaluated against one or more design implementation files corresponding to the design.
    Type: Application
    Filed: June 27, 2022
    Publication date: May 11, 2023
    Inventors: Edward CARLISLE, IV, Jonathan GRAF, Scott HARPER, Steven FREDERIKSEN
  • Publication number: 20230087217
    Abstract: A computer system traces an original electronic design automation (EDA) implementation process for electronic hardware designs. The original EDA implementation process includes multiple subprocesses to convert a hardware model to a physically-realized electronic circuit. The system inputs a cryptographic key and design information that includes the hardware model, constraints, properties, implementation settings, and other directives for directing the conversion. The cryptographic key and design information are processed to generate a sequence of instructions to execute and provide traceability of each subprocess.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 23, 2023
    Inventors: Ali Asgar SOHANGHPURWALA, Scott HARPER, Jonathan GRAF, Carlton FRALEY, Alan COOK, Timothy DUNHAM
  • Patent number: 7902866
    Abstract: A method, and system, for reconfiguring an FPGA which has a static region and a dynamic region is provided. The method includes the steps of: (a) providing a dynamic module library having information of predetermined modules; (b) receiving a reconfiguration request external to the FPGA; (c) computing reconfiguration of the FPGA at a predetermined location using predetermined module information from the dynamic module library and the reconfiguration request, and generating reconfigurable partial bitstreams; and (d) sending partial bitstreams from the predetermined location to the FPGA to perform the reconfiguration.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: March 8, 2011
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventors: Cameron Patterson, Peter Athanas, John K. Bowen, Timothy G. Dunham, Justin D. Rice, Matthew T. Shelburne, Jorge A. Suris Pletri, Jonathan Graf