Patents by Inventor Jonathan James Ashley
Jonathan James Ashley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9171571Abstract: An embodiment of a read channel includes a filter, an interpolator, a recovery circuit, an error detector, a reverse interpolator, and a filter calibrator. The filter is operable to receive a raw sample of a signal and a coefficient-correction value, generate a filtered sample from the raw sample and a pre-established coefficient, and change the coefficient in response to the coefficient-correction value. The interpolator is operable to interpolate the filtered sample, and the recovery circuit is operable to generate a data symbol from the interpolated sample. The error detector is operable to generate an ideal sample from the data symbol and to generate a difference between the ideal sample and the interpolated sample, and the reverse interpolator is operable to reverse interpolate the difference. The filter calibrator is operable to receive the raw sample and to generate the coefficient-correction value from the raw sample and the reverse-interpolated difference.Type: GrantFiled: February 26, 2007Date of Patent: October 27, 2015Assignee: STMicrolectronics, Inc.Inventors: Hakan Ozdemir, Jonathan James Ashley
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Patent number: 8407571Abstract: Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).Type: GrantFiled: August 26, 2009Date of Patent: March 26, 2013Assignee: Agere Systems LLCInventors: Jonathan James Ashley, Kelly Knudson Fitzpatrick, Erich Franz Haratsch
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Patent number: 8223827Abstract: A method and apparatus are provided for determining a plurality of filter tap weights or biases (or both) for a noise predictive filter used to generate one or more signal dependent branch metrics. A filter tap weight or filter bias (or both) are adaptively accumulated for each possible data condition. The data conditions may comprise, for example, each possible data pattern for a given data dependency length. The appropriate accumulated filter tap weight or bias to update can be selected based on a data condition associated with the current received data. The filter tap weights associated with a delay 0 tap can be adapted for each filter condition except for a single normalizing condition, whose corresponding delay 0 tap remains fixed.Type: GrantFiled: May 5, 2004Date of Patent: July 17, 2012Assignee: Agere Systems Inc.Inventors: Jonathan James Ashley, Keenan Terrell O'Brien, Richard Rauschmayer, Sumeet Sanghvi, Anne Q. Ye, Kaichi Zhang
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Patent number: 7937649Abstract: A reliability unit is provided for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.Type: GrantFiled: August 26, 2009Date of Patent: May 3, 2011Assignee: Agere Systems Inc.Inventors: Jonathan James Ashley, Kelly Knudson Fitzpatrick, Erich Franz Haratsch
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Patent number: 7865814Abstract: A path metric difference computation unit is disclosed for computing path differences through a multiple-step trellis. Path differences are computed between paths through a multiple-step trellis, wherein a first path is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period.Type: GrantFiled: August 26, 2009Date of Patent: January 4, 2011Assignee: Agere Systems Inc.Inventors: Jonathan James Ashley, Kelly Knudson Fitzpatrick, Erich Franz Haratsch
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Publication number: 20100050060Abstract: A path comparison unit is disclosed for determining paths in a trellis that compete with a survivor path. The disclosed path comparison unit comprises a first type functional unit comprising a multiplexer and a register to store one or more survivor bits associated with the survivor path; and at least two second type functional units, wherein each second type functional unit comprises a multiplexer and a logical circuit to compute at least one equivalence bit indicating whether the bit for a respective path and the bit for the survivor path are equivalent. Generally, the respective path is one or more of a win-lose path and a lose-win path.Type: ApplicationFiled: August 26, 2009Publication date: February 25, 2010Applicant: AGERE SYSTEMS INC.Inventors: Jonathan James Ashley, Kelly Knudson Fitzpatrick, Erich Franz Haratsch
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Patent number: 7646829Abstract: A composite data detector having first and second data detectors. The second detector of the invention starts in a known state and only runs as long as is necessary before being switched off and handing control back over to the smaller detector. Therefore, the composite data detector of the invention consumes less power than the known composite data detector and estimates bits with higher accuracy.Type: GrantFiled: December 23, 2004Date of Patent: January 12, 2010Assignee: Agere Systems, Inc.Inventors: Jonathan James Ashley, Harley F. Burger, Jr.
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Publication number: 20090319874Abstract: A reliability unit is disclosed for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.Type: ApplicationFiled: August 26, 2009Publication date: December 24, 2009Applicant: AGERE SYSTEMS INC.Inventors: Jonathan James Ashley, Kelly Knudson Fitzpatrick, Erich Franz Haratsch
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Publication number: 20090319875Abstract: A path metric difference computation unit is disclosed for computing path differences through a multiple-step trellis. The disclosed path metric difference computation unit computes differences between paths through a multiple-step trellis, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second of the plurality of paths is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third of the plurality of paths is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle.Type: ApplicationFiled: August 26, 2009Publication date: December 24, 2009Applicant: AGERE SYSTEMS INC.Inventors: Jonathan James Ashley, Kelly Knudson Fitzpatrick, Erich Franz Haratsch
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Publication number: 20090313531Abstract: Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).Type: ApplicationFiled: August 26, 2009Publication date: December 17, 2009Applicant: AGERE SYSTEMS INC.Inventors: Jonathan James Ashley, Kelly Knudson Fitzpatrick, Erich Franz Haratsch
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Patent number: 7607072Abstract: Methods and apparatus are provided for performing Soft-Output Viterbi Algorithm (SOVA) detection at higher data rates than achievable with conventional designs.Type: GrantFiled: January 28, 2005Date of Patent: October 20, 2009Assignee: Agere Systems Inc.Inventors: Jonathan James Ashley, Kelly Knudson Fitzpatrick, Erich Franz Haratsch
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Patent number: 7561649Abstract: A method and apparatus are disclosed for detecting a synchronization mark in a received signal. The received signal is processed to compensate for a DC bias in the received signal, such as subtracting an average of a block of received samples from each sample in the block. A distance metric, such as a sum of square differences, is computed between the DC compensated received signal and an ideal version of the received signal expected when reading the synchronization mark. The synchronization mark is detected if the distance metric satisfies predefined criteria. The ideal version of the received signal can optionally be processed to compensate for a DC bias in the synchronization mark. A search for the synchronization mark search can be limited to time cycles that match a known phase.Type: GrantFiled: April 30, 2004Date of Patent: July 14, 2009Assignee: Agere Systems Inc.Inventors: Jonathan James Ashley, Ching-Fu Wu, Kaichi Zhang
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Patent number: 7516394Abstract: Methods and apparatus are provided for a combined encoder/syndrome computer with a programmable parity level. In one embodiment, a circuit is disclosed that generates check symbols during an encoding operation and generates error syndromes during a decoding operation. The circuit comprises a plurality of subfilters grouped into a multiple degree polynomial filter, where the number of multiple degree subfilters is less than a maximum number of symbols of redundancy.Type: GrantFiled: March 14, 2005Date of Patent: April 7, 2009Assignee: Agere Systems Inc.Inventors: Jonathan James Ashley, Clifton Williamson
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Patent number: 7487432Abstract: A reduced-state Viterbi detector is disclosed that precomputes branch metrics for a multiple-step trellis for speculative sequences of one or more channel symbols; selects one of said precomputed branch metrics for multi-step state transitions based on at least one multi-step decision from at least one corresponding state; and selects a path having a best path metric for a given state.Type: GrantFiled: May 25, 2004Date of Patent: February 3, 2009Assignee: Agere Systems Inc.Inventors: Jonathan James Ashley, Erich Franz Haratsch
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Patent number: 6141783Abstract: The present invention is an encoder and decoder that eliminate all infinitely propagating error sequences for many sets of taps. The encoder includes an input circuit operable to receive an unencoded data signal and an encoding circuit, coupled to the input circuit, operable to generate the encoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel. The decoder includes an input circuit operable to receive an encoded data signal and a decoding table, coupled to the input circuit, operable to generate the decoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel.Type: GrantFiled: April 10, 1998Date of Patent: October 31, 2000Assignee: International Business Machines CorporationInventors: Jonathan James Ashley, Mario Blaum, Brian Harry Marcus, Constantin Michael Melas
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Patent number: 6016330Abstract: The present invention is an apparatus and method for detecting a codeword from a data stream comprising a series of sequences of samples representing intensities of an analog signal. The data stream may be output from, for example, a holographic storage device. The data stream is encoded using a code which may be represented by a trellis. One embodiment of the present invention uses a block encoded balanced code, one embodiment uses a finite state encoded balanced code and another embodiment uses a finite-state encoded DC free code. Each code defines a set of codewords which meet the constraints of the code. The codewords are detected from a sequence of samples by selecting the codeword having the greatest correlation with the sequence of samples. In a preferred embodiment, the correlation detection is implemented using the Viterbi process to iteratively determine correlations and codewords for each state at each level of the trellis based on the correlations at the preceding level of the trellis.Type: GrantFiled: October 18, 1996Date of Patent: January 18, 2000Assignee: International Business Machines CorporationInventors: Jonathan James Ashley, Brian Harry Marcus
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Patent number: 5969649Abstract: Disclosed are robust Resync patterns for insertion into a run length limited (d,k) encoded channel bit stream, which Resync pattern may be recovered from the RLL (d,k) encoded bit stream without being confused with data. The Resync pattern includes at least one string of consecutive "0"s which exceeds the RLL (k) constraint, and is inserted into the channel bit stream RLL data codewords. The RLL code excludes certain patterns representing a bit shift from the Resync pattern of one or both "1" bits adjacent to the string of "0" bits, shifted to shorten the Resync pattern to within the (k) constraint. Additionally, the Resync pattern may have two different aspects, one of which is the string of "0"s violating the constraints of the RLL code, and another which is specifically excluded from the RLL code, such as an excluded concatenated sequence of a VFO bit pattern of predetermined length or greater.Type: GrantFiled: February 17, 1998Date of Patent: October 19, 1999Assignee: International Business Machines CorporationInventors: Jonathan James Ashley, Glen Alan Jaquette, Brian Harry Marcus, Paul Joseph Seger
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Patent number: 5946354Abstract: A hard disk drive read circuit for d=1 run length limited (RLL) encoded data which processes multiple consecutive data samples in parallel. The circuit of the present invention receives an analog signal from the read head of the hard disk drive. The circuit comprises a plurality of digital detection channels, coupled to the analog signal, each channel outputting an alternate bit of digital data represented by the analog signal. A timing circuit, coupled to the plurality of digital detection channels, generates a plurality of timing signals controlling the plurality of digital detection channels. The timing circuit derives timing information from one of the digital detection channels. The d=1 RLL code is modified so that there are at most nine consecutive 0's in the digital data output by the digital detection channel from which the timing circuit derives the timing information. An encoder generates the encoded digital data to be recorded on the hard disk drive.Type: GrantFiled: October 18, 1996Date of Patent: August 31, 1999Assignee: International Business Machines CorporationInventors: Jonathan James Ashley, Brian Harry Marcus, Constantin Michael Melas
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Patent number: 5907581Abstract: A one-dimensional data stream is encoded into a two-dimensional data array with reduced high frequency components, for recording on a two-dimensional recording device, such as a holographic storage device. A two-dimensional data array read from the two-dimensional recording device is decoded into the original one-dimensional data stream. To encode, a one-dimensional data stream is partitioned into a plurality of chunks of data. Each chunk of data is partitioned into a plurality of groups of bits. Each group of bits is encoded into a two dimensional data array according to a predefined constraint. A plurality of two-dimensional data arrays are concatenated into a data strip. A plurality of data strips are then assembled into a complete two-dimensional data block. To decode, a two-dimensional data stream is partitioned into multiple small two-dimensional arrays. Each array is decoded into a multi-bit group. In one embodiment, this decoding is a function of other nearby groups.Type: GrantFiled: September 27, 1996Date of Patent: May 25, 1999Assignee: International Business Machines CorporationInventors: Jonathan James Ashley, Brian Harry Marcus