Patents by Inventor Jonathan Lueker
Jonathan Lueker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070297212Abstract: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.Type: ApplicationFiled: August 29, 2007Publication date: December 27, 2007Inventors: Richard Coulson, Jonathan Lueker, Robert Faber
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Publication number: 20070292855Abstract: A device having a functionalized electrode having a probe molecule, wherein the device has an ability to electrically detect a molecular binding event between the probe molecule and a target molecule by a polarization change of the functionalized electrode is disclosed. The device could also include an unfunctionalized electrode that does not have the probe molecule and the device could have an ability to electrically detect the molecular binding event between the probe molecule and the target molecule by a polarization change between the functionalized electrode and the unfuctionalized electrode.Type: ApplicationFiled: August 19, 2005Publication date: December 20, 2007Applicant: Intel CorporationInventors: Valery Dubin, Florian Gstrein, Jonathan Lueker
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Publication number: 20070283058Abstract: A concurrent asynchronous USB 2.0 data stream destuffer and separator with variable-width bit-wise memory controller is described. A parallel stream bit destuffer module identifies in parallel one or more stuffed bits in a decoded data field of a received data stream using a six-bit sliding window. The stuffed bits are bits that were inserted into the received USB data stream by a transmitter to force data transitions in the received USB data stream. A data separator module separates the one or more stuffed bits from a plurality of valid data bits in the decoded data field. A memory module generates an incremental pointer value representative of the number of valid bits and writes the plurality of valid data bits from the decoded data field into a variable sized bit-wise memory structure.Type: ApplicationFiled: December 13, 2006Publication date: December 6, 2007Inventors: Dean Warren, Jonathan Lueker
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Patent number: 7283382Abstract: The effects of a self-erase phenomenon when accessing imprinted ferroelectric memory cells that have non-conductive electrode interfaces that reduce remnant polarization and decrease signal margin are eliminated. A self-erase control pulse asserted after an access pulse is utilized. The self-erase control pulse has a magnitude sufficient to offset a remnant charge on the non-conductive electrode interfaces after the removal of the access pulse.Type: GrantFiled: June 29, 2005Date of Patent: October 16, 2007Assignee: Intel CorporationInventors: Hitesh Windlass, Jonathan Lueker
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Publication number: 20070002665Abstract: The effects of a self-erase phenomenon when accessing imprinted ferroelectric memory cells that have non-conductive electrode interfaces that reduce remnant polarization and decrease signal margin are eliminated. A self-erase control pulse asserted after an access pulse is utilized. The self-erase control pulse has a magnitude sufficient to offset a remnant charge on the non-conductive electrode interfaces after the removal of the access pulse.Type: ApplicationFiled: June 29, 2005Publication date: January 4, 2007Inventors: Hitesh Windlass, Jonathan Lueker
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Publication number: 20060087875Abstract: Briefly, voltages to write a memory cell are adjusted if the memory cell is determined to be imprinted. In one embodiment, a positive voltage not including zero is applied to one of a bit line and a word line and a negative voltage not including zero is applied to another of the bit line and the word line to write a specified logic state to an imprinted memory cell. Neighboring cells do not receive disturb voltages in excess of a disturb voltage threshold.Type: ApplicationFiled: October 25, 2004Publication date: April 27, 2006Inventors: Jonathan Lueker, Richard Coulson
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Publication number: 20060075168Abstract: A concurrent asynchronous USB 2.0 data stream destuffer and separator with variable-width bit-wise memory controller is described. A parallel stream bit destuffer module identifies in parallel one or more stuffed bits in a decoded data field of a received data stream using a six-bit sliding window. The stuffed bits are bits that were inserted into the received USB data stream by a transmitter to force data transitions in the received USB data stream. A data separator module separates the one or more stuffed bits from a plurality of valid data bits in the decoded data field. A memory module generates an incremental pointer value representative of the number of valid bits and writes the plurality of valid data bits from the decoded data field into a variable sized bit-wise memory structure.Type: ApplicationFiled: April 19, 2005Publication date: April 6, 2006Inventors: Dean Warren, Jonathan Lueker
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Publication number: 20050288902Abstract: Briefly, one or more memory access parameters used to access a memory cell are adjusted based on a sensed operating temperature. In one embodiment, a pulse width of an access voltage is increased as the operating temperature decreases below a threshold. In another embodiment, a drive voltage is decreased as the operating temperature increases.Type: ApplicationFiled: June 25, 2004Publication date: December 29, 2005Inventors: Richard Coulson, Jonathan Lueker
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Publication number: 20050207206Abstract: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.Type: ApplicationFiled: May 11, 2005Publication date: September 22, 2005Inventors: Richard Coulson, Jonathan Lueker, Robert Faber
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Patent number: 6731687Abstract: A method for dynamically balancing a serial data link is disclosed. The serial data link includes a first transmission line and a second transmission line. The method includes the steps of creating a DC offset voltage between the first and second transmission lines when the serial data link is in an idle state. When the serial data link is in use to carry data, the DC offset voltage between the first and second transmission lines is removed.Type: GrantFiled: October 22, 1999Date of Patent: May 4, 2004Assignee: Intel CorporationInventor: Jonathan Lueker
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Patent number: 6182141Abstract: A transparent proxy. In a computer system, a layered service provider intercepts a communications request from a client application in the native protocol of the communications request wherein the communications request requests communication with a remote server. The service provider bundles and passes the communications request to a predetermined port. A transparent proxy application listening on the predetermined port receives the communications request in the native protocol of the request and establishes the requested communication.Type: GrantFiled: December 20, 1996Date of Patent: January 30, 2001Assignee: Intel CorporationInventors: Scott B. Blum, Jonathan Lueker
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Patent number: 5430660Abstract: A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included.Type: GrantFiled: June 1, 1993Date of Patent: July 4, 1995Assignee: Tektronix, Inc.Inventors: Jonathan Lueker, John Hengeveld, Brad Needham, Burt Price, Jim Schlegel, Mehrab Sedeh
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Patent number: 5252977Abstract: A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included.Type: GrantFiled: March 9, 1992Date of Patent: October 12, 1993Assignee: Tektronix, Inc.Inventors: Jonathan Lueker, John Hengeveld, Brad Needham, Burt Price, Jim Schlegel, Mehrab Sedeh
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Patent number: 5249132Abstract: A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included.Type: GrantFiled: March 9, 1992Date of Patent: September 28, 1993Assignee: Tektronix, Inc.Inventors: Jonathan Lueker, John Hengeveld, Brad Needham, Burt Price, Jim Schlegel, Mehrab Sedeh
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Patent number: 5224129Abstract: A digital architecture for a pulse generator provides a method of synchronizing signals of the pulse generator. The pulse generator has a timebase card, a microprocessor and a plurality of pulse cards. The microprocessor controls the parameters of the timebase card and pulse cards, and the timebase card provides a common master clock signal to all of the pulse cards determined by a triggerable voltage controlled oscillator that has two sources of frequency control voltage, an internal DAC for absolute frequency and a frequency comparison circuit for synchronization with an external timebase. The pulse cards produce pulses, either singly or in bursts, with the leading and trailing edges being separately positionable using quantum, sliver and vernier controls. A pattern RAM on each pulse card provides a pulse pattern that provides an approximation of the desired pulses to one quantum, and repeated iterations through the pattern RAM provide bursts of pulses.Type: GrantFiled: March 9, 1992Date of Patent: June 29, 1993Assignee: Tektronix, Inc.Inventors: Jonathan Lueker, John Hengeveld, Brad Needham, Burt Price, Jim Schlegel, Mehrab Sedeh
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Patent number: 5208598Abstract: A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included.Type: GrantFiled: October 31, 1990Date of Patent: May 4, 1993Assignee: Tektronix, Inc.Inventors: Jonathan Lueker, John Hengeveld, Brad Needham, Burt Price, Jim Schlegel, Mehrab Sedeh
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Patent number: 4924110Abstract: A step generator for producing steps having constant edge parameters while driving varying loads includes a pair of DC coupled low speed diode switches for slowly switching the output load current. A pair of capacitors provide an AC coupled high speed input for rapidly, but temporarily, switching the output load current until the sustaining action of the low speed diode switch has occurred. A pair of resistor divider circuits in each of the low speed diode switches maintains a relatively constant reverse bias voltage across the diodes coupled to the capacitors. The high speed switching threshold is maintained at a relatively constant level which produces an output voltage step with constant edge parameters and no overshoot.Type: GrantFiled: September 8, 1988Date of Patent: May 8, 1990Assignee: Tektronix, Inc.Inventors: John B. Rettig, Jonathan Lueker, John E. Carlson, Stanley P. Kaveckis, Roy W. Lewallen