Abstract: A variable-delay circuit on an integrated circuit is used to delay a periodic strobe signal. In normal operation, the strobe signal can be shifted 90 degrees to center it within a data bit cell. In test mode, it can also be shifted up to 270 degrees in N increments to measure the effective input latch setup and hold timings. The variable-delay circuit comprises a voltage-mixing interpolator circuit to produce phase delays in N increments. The variable-delay circuit can incorporate an existing delay locked loop. Also described are an electronic system, a data processing system, and various methods of performing on-chip testing and calibration.

Abstract: A method for testing an MOS, dynamic random-access memory employing full capacitance dummy cells is described. During probe testing a potential higher than the reference potential is applied to the dummy cells when reading binary zeroes from the memory and a potential lower than the reference potential is applied to the dummy cells when reading binary zeroes from the memory. This testing procedure detects weak cells and amplifiers and helps present the packaging of defective parts. In addition, a simplified means for programming redundant elements is described which requires substantially less substrate area than previous methods.

Abstract: An MOS dynamic RAM organized in a byte-wide arrangement is described. An internal bus is used for multiplexed column address signals and data. Other multiplexing reduced the lines associated with the input/output circuits. A unique power-on circuit automatically resets clock generators if they are not operative after power is applied.