Abstract: Apparatus and methods to efficiently process packet data are disclosed. In one embodiment, a microcode engine designed to efficiently parse packet data may use instructions that are tailored to parse packet data fields of a data packet having nested protocols. The microcode engine design and the instruction set may enable highly efficient packet processing while preserving flexibility as to the packet protocols that can be processed. The implementation can be both specific to a packet processing task while allowing reprogramming to perform a different specific task simply by changing the instructions. The microcode engine may execute instructions in a single clock cycle or in a pipelined configuration to generate appropriately modified packet data. The microcode engine may operate in lock step with received packet data.

Abstract: A stackable data cell switch architecture includes a plurality of switch modules coupled in series and forming a bidirectional data transmission loop. Each switch module includes a data cell switch such as an asynchronous transfer mode (ATM) switch, a first transceiver coupled to the data cell switch for receiving data cells from and transmitting data cells to an adjacent switch module in a first transmission direction, and a second transceiver coupled to the data cell switch for receiving data cells from and transmitting data cells to an adjacent switch module in a second transmission direction.

Abstract: Egress processing of asynchronous transfer mode (ATM) cells is performed by an egress processor (18) that receives ATM cells from an ingress processor (16) through a cell bus (20). ATM cells are received in the egress processor (18) through an egress FIFO buffer (32) and placed within available space in an ECELL memory (38) through a single cell FIFO buffer (34) as controlled by a cell loader (36). A linker (44) chains together ATM cells, no matter where they are located in the ECELL memory (38), corresponding to a particular call into a specific packet by placing pointer information within each ATM cell of a specific packet such that each ATM cell points to the next ATM cell within the packet. The linker (44) places the cell location of the first cell of the packet into a packet FIFO buffer (52) of a cell location buffer (48).

Abstract: A system (10) is provided for processing data such that the rate at which events occur in a network for a particular user does not exceed a predetermined rate. A request to allow a potential event is received by a sequencer (12). Event rate information is retrieved from random access memory (30) for the particular user and provided to plurality of registers (18). A reference level is generated by reference level generating circuitry (16) for use in determining whether to allow the potential event to occur. A determination is made by comparison circuitry (24) as to whether to allow the potential event based on the reference level and the retrieved event rate information. Function generating circuitry (20) updates the event rate information based on the retrieved event rate information, the reference level, and an output of comparison circuitry (24).