Abstract: Methods and systems for ultrasound imaging and beamforming with a matrix array of transducer elements are provided. Receive signals of each transducer array element are amplified. The amplified receive signal of each transducer array element is digitized. A delay and weight are applied on the amplified and digitized receive signals. The amplified, digitized, delayed, and weighted receive signals are summed across all transducer elements of the matrix array to form a dynamically focused receive beam. An application specific integrated circuit (ASIC) that is integrated with the matrix array of transducer elements performs such steps.

Abstract: Described herein are methods and systems for testing transducers and associated integrated circuits. In some cases, a method or system described herein can comprise modulating a bias voltage using a test signal in order to produce a modulated bias voltage signal useful in testing a plurality of transducers of a transducer array in parallel.

Abstract: A capacitive digital to analog converter (DAC) includes a first switching device that receives first, second, third, and fourth reference potentials at respective inputs and that selectively connects one of the first, second, third, and fourth reference potentials to a first output. The first and second reference potentials are approximately equal. The third and fourth reference potentials are approximately equal. A first capacitor is connected between the first output and a common node. A second switching device receives the first, second, third, and fourth reference potentials at respective inputs and selectively connects one of the first, second, third, and fourth reference potentials to a second output. A second capacitor is connected between the second output and the common node.

Abstract: A system includes an analog to digital converter (ADC) that samples an analog input signal as received by a first channel of a plurality of channels, samples the analog input signal as received by at least a second channel of the plurality of channels, and outputs a plurality of digital samples including a first set and a second set of digital samples of the analog input signal corresponding to the first channel and the second channel, respectively. A filter receives the first and second sets of digital samples, up-samples each of the first and second sets of digital samples, filters the up-sampled first set of digital samples and the up-sampled second set of digital samples, and outputs a first digital output signal and at least a second digital output signal based on the filtered first set of digital samples and the filtered second set of digital samples, respectively.

Abstract: A system includes a switched capacitor circuit and a stabilizing circuit. The switched capacitor circuit receives a reference voltage from a reference node, transitions from a first state to a second state, and draws or supplies a switched capacitor charge from or to the reference node in response to transitioning from the first state to the second state. The second state is a function of the first state, an input of the switched capacitor circuit, or a combination of both. The stabilizing circuit stabilizes the reference voltage by supplying or drawing a stabilizing charge to or from the reference node based on the first and second states of the switched capacitor circuit.

Abstract: A capacitive digital to analog converter (DAC) includes a first switching device that receives first, second, third, and fourth reference potentials at respective inputs and that selectively connects one of the first, second, third, and fourth reference potentials to a first output. The first and second reference potentials are approximately equal. The third and fourth reference potentials are approximately equal. A first capacitor is connected between the first output and a common node. A second switching device receives the first, second, third, and fourth reference potentials at respective inputs and selectively connects one of the first, second, third, and fourth reference potentials to a second output. A second capacitor is connected between the second output and the common node.

Abstract: A capacitive digital to analog converter (DAC) includes: a first capacitor including a first terminal and a second terminal, the second terminal connected to a common node; a first switching device: including a third terminal connected to the first terminal of the first capacitor; including fourth, fifth, sixth, and seventh terminals that are connected to first, second, third, and fourth reference potentials, respectively; and selectively connecting the third terminal to the fourth, fifth, sixth, and seventh terminals; a second capacitor including an eighth terminal and a ninth terminal, the ninth terminal connected to the common node; and a second switching device: including a tenth terminal connected to the eighth terminal of the second capacitor; including eleventh, twelfth, thirteenth, and fourteenth terminals that are connected to the first, second, third, and fourth reference potentials, respectively; and selectively connecting the tenth terminal to the eleventh, twelfth, thirteenth, and fourteenth term