Abstract: An interactive sound generating greeting card having two separate and distinct components, one being an outer greeting card which serves as a pocket or cavity with a slot located thereon providing access to the pocket or cavity and the other being an inner greeting card which is sized to partially fit into the cavity in the outer greeting card. A sound module is contained and concealed within the outer greeting card cavity, including a switch mechanism. The inner greeting card and switch mechanism work in combination to control the playback of a digital audio file stored on the sound module such that when the inner greeting card is contained within the cavity of the outer greeting card, playback of the digital audio file is deactivated and when the inner greeting card is removed from the cavity of the outer greeting card, playback of the digital audio file is activated.

Abstract: The interactive flap sensor activated greeting card of the present invention contains an audio module and a series of “window flaps” across the inside of the greeting card. When the greeting card is opened, a short audio prompt instructs the user to open a series of flaps inside the card to hear further audio messages or sound clips that correlate with the art work inside the card. When each flap is opened, a different audio file is played. The sound module is programmed to react to the card opening and then to trigger additional individual sounds each time one of the flaps of the card is opened. In another embodiment, the greeting card contains a series of flaps wherein opening one flap reveals another flap, and so on. Once the last flap is opened, a short audio recording is activated.

Abstract: An improved method and apparatus for performing single-cycle operations (such as for example Maximum a Posteriori, i.e. MAP decode) in digital processors is disclosed. In one exemplary configuration, a processor is fitted with a specialized instruction and extension Arithmetic Logic Unit (ALU) to efficiently perform the forward and reverse transition trellis metric updates as well as the Log Likelihood ratio calculation in order to accelerate the decoding of Turbo-encoded data sequences. The processor executes software comprising the single operand instruction to perform Turbo decoding with the efficiency comparable to a dedicated hardware implementation. The programmable apparatus can be readily reprogrammed to accommodate evolving standards.

Abstract: An improved method and apparatus for performing single-cycle operations (such as for example Maximum a Posteriori, i.e. MAP decode) in digital processors is disclosed. In one exemplary configuration, a processor is fitted with a specialized instruction and extension Arithmetic Logic Unit (ALU) to efficiently perform the forward and reverse transition trellis metric updates as well as the Log Likelihood ratio calculation in order to accelerate the decoding of Turbo-encoded data sequences. The processor executes software comprising the single operand instruction to perform Turbo decoding with the efficiency comparable to a dedicated hardware implementation. The programmable apparatus can be readily reprogrammed to accommodate evolving standards.

Abstract: An improved method and apparatus for performing single-cycle operations (such as for example Maximum a Posteriori, i.e. MAP decode) in digital processors is disclosed. In one exemplary configuration, a processor is fitted with a specialized instruction and extension Arithmetic Logic Unit (ALU) to efficiently perform the forward and reverse transition trellis metric updates as well as the Log Likelihood ratio calculation in order to accelerate the decoding of Turbo-encoded data sequences. The processor executes software comprising the single operand instruction to perform Turbo decoding with the efficiency comparable to a dedicated hardware implementation. The programmable apparatus can be readily reprogrammed to accommodate evolving standards.