Patents by Inventor Jonathon Robert Carstens

Jonathon Robert Carstens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10680367
    Abstract: Embodiments of the disclosure are directed to a linear edge connector assembly for connecting to a substrate diving board of a mother board. The linear edge connector assembly can include an electrical interface to electrically connect the contacts on the diving board to one or more conducts of a cable bundle. The linear edge connector assembly can also include a retaining force mechanism. The retaining force mechanism can include a torsional spring, a spring loaded hooking mechanism, or a spring loaded cam and lever. In some embodiments, the linear edge connector can include a notch to receive a latch connected to a bolster plate on the mother board.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Feifei Cheng, Kuang C. Liu, Michael Garcia, Eric W. Buddrius, Kevin J. Ceurter, Anthony P. Valpiani, Jonathon Robert Carstens
  • Patent number: 10260961
    Abstract: Disclosed herein are integrated circuit (IC) packages with temperature sensor traces, and related systems, devices, and methods. In some embodiments, an IC package may include a package substrate and an IC die disposed on the package substrate, wherein the package substrate includes a temperature sensor trace, and an electrical resistance of the temperature sensor trace is representative of an equivalent temperature of the temperature sensor trace.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Shelby Ferguson, Rashelle Yee, Russell S. Aoki, Michael Hui, Jonathon Robert Carstens, Joseph J. Jasniewski
  • Patent number: 10178763
    Abstract: Disclosed herein are apparatus, systems, and methods for warpage mitigation in printed circuit board (PCB) assemblies. In some embodiments, a PCB assembly for warpage mitigation may include: a PCB; an interposer disposed on the PCB, wherein the interposer has a first face and an opposing second face, the first face is disposed between the second face and the PCB, conductive contacts are disposed at the second face, solder is disposed on the conductive contacts, the interposer includes a first heater trace proximate to the conductive contacts, and, when a first power is dissipated in the first heater trace, the first heater trace is to generate heat to cause the solder disposed on the conductive contacts to melt; wherein the PCB includes a second heater trace.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Rashelle Yee, Russell S. Aoki, Shelby Ferguson, Michael Hui, Jonathon Robert Carstens, Joseph J. Jasniewski, Kevin J. Ceurter
  • Patent number: 9825387
    Abstract: Embodiments of the present disclosure are directed to a linear edge connector assembly and corresponding bolster plate features for receiving and securing a linear edge connector assembly. Embodiments of the disclosure are directed to a linear edge connector assembly that includes a grooved and indented receiver that can receive a spring loaded ball on the bolster plate. In embodiments, the linear edge connector assembly can include a magnetic element to create a magnetic attraction to magnetic elements on the bolster plate, such as a press-fit ball or a U-shaped hardstop. In some embodiments, the linear edge connector assembly includes a screw or push pin that can be received by a receiver on the bolster plate. The receiver can include a thread or friction fit receiver.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Feifei Cheng, Kuang C. Liu, Michael Garcia, Eric W. Buddrius, Kevin J. Ceurter, Jonathon Robert Carstens
  • Publication number: 20170288331
    Abstract: Embodiments of the present disclosure are directed to a linear edge connector assembly and corresponding bolster plate features for receiving and securing a linear edge connector assembly. Embodiments of the disclosure are directed to a linear edge connector assembly that includes a grooved and indented receiver that can receive a spring loaded ball on the bolster plate. In embodiments, the linear edge connector assembly can include a magnetic element to create a magnetic attraction to magnetic elements on the bolster plate, such as a press-fit ball or a U-shaped hardstop. In some embodiments, the linear edge connector assembly includes a screw or push pin that can be received by a receiver on the bolster plate. The receiver can include a thread or friction fit receiver.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Inventors: Feifei Cheng, Kuang C. Liu, Michael Garcia, Eric W. Buddrius, Kevin J. Ceurter, Jonathon Robert Carstens
  • Publication number: 20170288330
    Abstract: Embodiments of the disclosure are directed to a linear edge connector assembly for connecting to a substrate diving board of a mother board. The linear edge connector assembly can include an electrical interface to electrically connect the contacts on the diving board to one or more conducts of a cable bundle. The linear edge connector assembly can also include a retaining force mechanism. The retaining force mechanism can include a torsional spring, a spring loaded hooking mechanism, or a spring loaded cam and lever. In some embodiments, the linear edge connector can include a notch to receive a latch connected to a bolster plate on the mother board.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Applicant: Intel Corporation
    Inventors: Feifei Cheng, Kuang C. Liu, Michael Garcia, Eric W. Buddrius, Kevin J. Ceurter, Anthony P. Valpiani, Jonathon Robert Carstens
  • Publication number: 20170178994
    Abstract: Disclosed herein are integrated circuit (IC) package support structures, and related systems, devices, and methods. In some embodiments, an IC package support structure may include a first heater trace, and a second heater trace, wherein the second heater trace is not conductively coupled to the first heater trace in the IC package support structure.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Michael Hui, Rashelle Yee, Jonathan Thibado, Daniel P. Carter, Shelby Ferguson, Anthony P. Valpiani, Russell S. Aoki, Jonathon Robert Carstens, Joseph J. Jasniewski, Harvey R. Kofstad, Michael Brazel, Tracy Clack, Viktor Vogman, Penny Woodcock, Kevin J. Ceurter, Hongfei Yan
  • Publication number: 20170176260
    Abstract: Disclosed herein are integrated circuit (IC) packages with temperature sensor traces, and related systems, devices, and methods. In some embodiments, an IC package may include a package substrate and an IC die disposed on the package substrate, wherein the package substrate includes a temperature sensor trace, and an electrical resistance of the temperature sensor trace is representative of an equivalent temperature of the temperature sensor trace.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Shelby Ferguson, Rashelle Yee, Russell S. Aoki, Michael Hui, Jonathon Robert Carstens, Joseph J. Jasniewski
  • Publication number: 20170181271
    Abstract: Disclosed herein are apparatus, systems, and methods for warpage mitigation in printed circuit board (PCB) assemblies. In some embodiments, a PCB assembly for warpage mitigation may include: a PCB; an interposer disposed on the PCB, wherein the interposer has a first face and an opposing second face, the first face is disposed between the second face and the PCB, conductive contacts are disposed at the second face, solder is disposed on the conductive contacts, the interposer includes a first heater trace proximate to the conductive contacts, and, when a first power is dissipated in the first heater trace, the first heater trace is to generate heat to cause the solder disposed on the conductive contacts to melt; wherein the PCB includes a second heater trace.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Rashelle Yee, Russell S. Aoki, Shelby Ferguson, Michael Hui, Jonathon Robert Carstens, Joseph J. Jasniewski, Kevin J. Ceurter