Abstract: A CMOS image sensor and a method for forming the same are provided. According to the method, a gate insulating layer and a doped polysilicon layer which are sequentially stacked on a substrate are patterned to form a transfer gate and a reset gate set apart from each other. A floating diffusion layer between the transfer gate and the reset gate, a light receiving element at a side of the transfer gate away from and opposite to the floating diffusion layer and a source/drain region at a side of the reset gate away from and opposite to the floating diffusion layer are formed. An insulation layer and a mold layer are sequentially formed on an entire surface of the substrate, and the mold layer is planarized until the insulation layer is exposed. The exposed insulation layer is removed to further expose an upper surface of the gates. A selective silicidation process is carried out using a metal gate layer to form a metal gate silicide on the exposed gate.

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor comprises a photodiode region generating electrical charges in response to incident light thereon. The CMOS image sensor further comprises a first floating diffusion layer adapted to receive the electrical charges from the photodiode region in response to a global transfer signal and a second floating diffusion region adapted to receive the electrical charges from the first floating diffusion region in response to a pixel selection signal.

Abstract: The present invention relates to a semiconductor device, and more particularly, to a test pattern for evaluating a process of silicide film formation. The test pattern in accordance with the present invention includes: a silicon substrate having an active region and a field region; a first pattern composed of a cross resistor pattern of a polycide layer formed on the field region; and a second pattern composed of polycide layer and a silicide layer formed on the active region. The second pattern includes: a pair of polycide patterns composed of a first polycide strip and a second polycide strip extended in parallel, being spaced from each other a predetermined interval on an insulating film formed on the active region; and an active silicide strip formed between the first polycide strip and the second polycide strip.

Abstract: The method of fabricating a semiconductor device having a dual-gate provides a semiconductor substrate with a gate insulating film formed on a first portion and a second portion thereof and a polysilicon layer formed on the gate insulating film. A first dopant of a first conductive type is implanted in the polysilicon layer covering the first portion, and a second dopant of a second conductive type is implanted in the polysilicon layer covering the second portion. Then, the polysilicon layer covering the first portion is selectively etched using a first mask to form a first gate, and a third dopant of the first conductive type is implanted to form source/drain LDD regions on both sides of the first gate. Thereafter, the polysilicon layer covering the second portion is selectively etched using a second mask to form a second gate, and a fourth dopant of the second conductive type is implanted to form source/drain LDD regions on both sides of the second gate.