Patents by Inventor Jongchol Kim

Jongchol Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11282695
    Abstract: A system for reconstructing wafer maps of semiconductor wafers includes: a processor; and memory having instructions stored thereon that, when executed by the processor, cause the processor to: receive test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and compute a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nuo Xu, Fan Chen, Weiyi Qi, Jongchol Kim, Jing Wang, Yang Lu, Woosung Choi
  • Publication number: 20190096659
    Abstract: A system for reconstructing wafer maps of semiconductor wafers includes: a processor; and memory having instructions stored thereon that, when executed by the processor, cause the processor to: receive test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and compute a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer.
    Type: Application
    Filed: August 21, 2018
    Publication date: March 28, 2019
    Inventors: Nuo Xu, Fan Chen, Weiyi Qi, Jongchol Kim, Jing Wang, Yang Lu, Woosung Choi
  • Publication number: 20110204434
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes, a gate structure having a gate dielectric layer, a gate electrode, and a spacer, which are each formed on a substrate, a first impurity area formed in a portion of the substrate located below the spacer, a second impurity area in contact with a sidewall of the first impurity area and formed in the substrate on both sides of the gate structure, and a dielectric pattern in contact with a portion of the first impurity area and formed on a sidewall of the second impurity area. At this time, the second impurity area may include an upper part with an upward-narrowing width and a lower part with a downward-narrowing width.
    Type: Application
    Filed: November 29, 2010
    Publication date: August 25, 2011
    Inventors: SEUNGHUN SON, Dongil Bae, Jongchol Kim, Seong-Cheol Paek
  • Patent number: 4828864
    Abstract: A powder suitable for the manufacture of a filling mass for bakery products comprising 15 to 25 parts of potato granules, 3 to 5 parts of fat, 3 to 6.5 parts of thickening agents and optionally 45 to 58 parts of sugar.
    Type: Grant
    Filed: October 18, 1985
    Date of Patent: May 9, 1989
    Assignee: Nestec S.A.
    Inventors: Peter Wellinga, Jongchol Kim