Abstract: The dual low-voltage driver circuit of the present invention operates as a buck-boost converter. If battery voltage is low (i.e., corresponding to a partially discharged battery), then “buck” section of the circuit is disabled and the “boost” section operates to increase the output voltage to a desired value. On the other hand, if the battery voltage is high (i.e., corresponding to a battery having a fresh charge), then the “boost” circuit is disabled and the “buck” section operates to reduce the output voltage to the desired value.

Abstract: A driver circuit includes three non-contiguous high-voltage wells formed within a low-voltage monolithic silicon substrate; a high-side driver circuit fabricated within each of the wells; a separate logic input path for each of the high-side driver circuits, each input path comprising a logic signal input terminal, a signal amplifier, a noise filter, a pulse generator, and a high-voltage level shifter; an output terminal for each driver circuit, each output terminal coupled to its associated driver circuit output through a separate mask-configurable, variable-value output resistor bank, which reduces the number of external components needed for driver circuitry; a startup circuit which prevents operation of an associated high-side switch during periods of line voltage instability; and embedded capacitor banks, each of which is in close proximity to a high-side switch, for reducing capacitive, resistive and inductance losses associated with long metal lines.

Abstract: A driver circuit includes three non-contiguous high-voltage wells formed within a low-voltage monolithic silicon substrate; a high-side driver circuit fabricated within each of the wells; a separate logic input path for each of the high-side driver circuits, each input path comprising a logic signal input terminal, a signal amplifier, a noise filter, a pulse generator, and a high-voltage level shifter; an output terminal for each driver circuit, each output terminal coupled to its associated driver circuit output through a separate mask-configurable, variable-value output resistor bank, which reduces the number of external components needed for driver circuitry; a startup circuit which prevents operation of an associated high-side switch during periods of line voltage instability; and embedded capacitor banks, each of which is in close proximity to a high-side switch, for reducing capacitive, resistive and inductance losses associated with long metal lines.

Abstract: In one embodiment, a method for detecting a load in a switched-mode power converter is provided. The switched-mode power converter includes high and low-side power switches which are configured to be driven respectively by high and low-side drive signals to provide a switching voltage. The high and low-side drive signals include a plurality of dead-time periods. The method includes monitoring a waveform of the switching voltage and at least one of the high and low-side drive signals. The monitored waveform of the switching voltage is compared to the monitored waveform of the at least one of the high and low-side drive signals to determine whether the switching voltage is high or low during at least one of the dead-time periods. A current measurement of the load is determined based on whether the switching voltage is high or low during the at least one of the dead-time periods.

Abstract: In one embodiment, a method for detecting a load in a switched-mode power converter is provided. The switched-mode power converter includes high and low-side power switches which are configured to be driven respectively by high and low-side drive signals to provide a switching voltage. The high and low-side drive signals include a plurality of dead-time periods. The method includes monitoring a waveform of the switching voltage and at least one of the high and low-side drive signals. The monitored waveform of the switching voltage is compared to the monitored waveform of the at least one of the high and low-side drive signals to determine whether the switching voltage is high or low during at least one of the dead-time periods. A current measurement of the load is determined based on whether the switching voltage is high or low during the at least one of the dead-time periods.

Abstract: A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.

Abstract: A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.

Abstract: A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.

Abstract: A circuit for minimizing audible click noise upon the startup of a Class D audio power amplifier. The amplifier including a power switching output stage and a driver for driving the output stage receiving a driving signal and a shutdown signal, the shutdown signal preventing switching of the output stage. The circuit including a comparator connected to the driver for generating the driving signal; an error amplifier receiving an audio input signal; a first feedback loop for connecting the output stage as input to an input of the error amplifier, an output of the error amplifier being connected to an output of the comparator; and a circuit coupled to the error amplifier preventing a capacitor connected to the error amplifier from excessively charging, thereby preventing noise in the output stage when the shutdown signal is removed.

Abstract: An integrated high-voltage linear amplifier IC with reduced power dissipation, faster operation, and small die size, comprising a low side well and a floating high side well; an error amplifier for receiving a noise signal; a level shifting circuit in the low side well for outputting a current mode error signal based on the noise signal to the high side well in differential current mode for noise reduction; and a drive circuit in the high side well. A voltage/current converter receives a voltage mode error signal based on the noise signal and supplies the current input signal. Current mirror circuitry and the drive circuit in the high side well outputs a sum current derived from the current mode error signal for driving external power devices.

Abstract: A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.

Abstract: An integrated high-voltage linear amplifier IC with reduced power dissipation, faster operation, and small die size, comprising a low side well and a floating high side well; an error amplifier for receiving a noise signal; a level shifting circuit in the low side well for outputting a current mode error signal based on the noise signal to the high side well in differential current mode for noise reduction; and a drive circuit in the high side well. A voltage/current converter receives a voltage mode error signal based on the noise signal and supplies the current input signal. Current mirror circuitry and the drive circuit in the high side well outputs a sum current derived from the current mode error signal for driving external power devices.