Patents by Inventor Jong Doo Joo
Jong Doo Joo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9349483Abstract: A one-time programmable (OTP) memory includes an OTP cell array including a plurality of OTP cells that each include a programming transistor configured to change irreversibly when programmed; a temperature compensation reference voltage generating unit configured to sense a temperature of the OTP cell memory and generate a reference voltage such that as the sensed temperature changes, the reference voltage generated by the temperature compensation reference voltage generating unit changes in a manner that is inversely proportional the change in the sensed temperature; and a temperature compensation operating voltage generating unit configured to receive the reference voltage to generate an operating voltage that is proportional to the reference voltage and is applied to the OTP cell array.Type: GrantFiled: November 12, 2014Date of Patent: May 24, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Jong-Doo Joo
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Publication number: 20150138870Abstract: A one-time programmable (OTP) memory includes an OTP cell array including a plurality of OTP cells that each include a programming transistor configured to change irreversibly when programmed; a temperature compensation reference voltage generating unit configured to sense a temperature of the OTP cell memory and generate a reference voltage such that as the sensed temperature changes, the reference voltage generated by the temperature compensation reference voltage generating unit changes in a manner that is inversely proportional the change in the sensed temperature; and a temperature compensation operating voltage generating unit configured to receive the reference voltage to generate an operating voltage that is proportional to the reference voltage and is applied to the OTP cell array.Type: ApplicationFiled: November 12, 2014Publication date: May 21, 2015Inventor: Jong-Doo JOO
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Patent number: 8797817Abstract: At least one example embodiment discloses a semiconductor device. The semiconductor device includes a first sense amplifier selectively connected between a first bit line and a second bit line, a second sense amplifier selectively connected between the first bit line and the second bit line, a first power supply circuit configured to provide a power supply voltage to the first sense amplifier in response to a first control signal, a second power supply circuit configured to provide a ground voltage to the second sense amplifier in response to a second control signal, and a switching circuit configured to selectively connect the first power supply circuit with the second power supply circuit in response to a third control signal.Type: GrantFiled: September 21, 2011Date of Patent: August 5, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Doo Joo, Cheol Ha Lee, Jung-Han Kim
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Patent number: 8315120Abstract: A semiconductor memory device can include a first driver configured to generate a pair of first sense amplifier driving signals having an activation period at a predetermined level during command execution; and a second driver that can be configured to generate a pair of second sense amplifier driving signals for increasing a driving strength of a pair of sense amplifiers when logic values of a pair of bit lines are constant during the command execution and decreasing the driving strength of the pair of sense amplifiers when the logic values of the pair of bit lines change.Type: GrantFiled: December 22, 2010Date of Patent: November 20, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Cheol Ha Lee, Jong Doo Joo, Jung-Han Kim
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Patent number: 8218375Abstract: An oscillation circuit includes an internal voltage generator and an oscillator. The internal voltage generator receives an external voltage and generates an internal voltage based on the external voltage. The internal voltage varies in linearly with an operational temperature. The oscillator generates a variable oscillation signal based on the internal voltage. A period of the variable oscillation signal varies in linearly with the operational temperature.Type: GrantFiled: January 19, 2010Date of Patent: July 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Doo Joo, Cheol-Ha Lee, Sang-Seok Lee
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Publication number: 20120081986Abstract: At least one example embodiment discloses a semiconductor device. The semiconductor device includes a first sense amplifier selectively connected between a first bit line and a second bit line, a second sense amplifier selectively connected between the first bit line and the second bit line, a first power supply circuit configured to provide a power supply voltage to the first sense amplifier in response to a first control signal, a second power supply circuit configured to provide a ground voltage to the second sense amplifier in response to a second control signal, and a switching circuit configured to selectively connect the first power supply circuit with the second power supply circuit in response to a third control signal.Type: ApplicationFiled: September 21, 2011Publication date: April 5, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Doo Joo, Cheol Ha Lee, Jung-Han Kim
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Patent number: 8067977Abstract: An active charge pump circuit may include a charge pump circuit, a control circuit, and a charge transfer circuit. The charge pump circuit may generate a charge pumping voltage in response to an active enable signal. The control circuit may generate a charge transfer control signal varying between a ground voltage and a boosted power supply voltage that is twice as much as a power supply voltage in response to the active enable signal. The charge transfer circuit may output the charge pumping voltage as an active voltage in response to the charge transfer control signal.Type: GrantFiled: April 7, 2009Date of Patent: November 29, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Jong-Doo Joo
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Publication number: 20110188333Abstract: A semiconductor memory device can include a first driver configured to generate a pair of first sense amplifier driving signals having an activation period at a predetermined level during command execution; and a second driver that can be configured to generate a pair of second sense amplifier driving signals for increasing a driving strength of a pair of sense amplifiers when logic values of a pair of bit lines are constant during the command execution and decreasing the driving strength of the pair of sense amplifiers when the logic values of the pair of bit lines change.Type: ApplicationFiled: December 22, 2010Publication date: August 4, 2011Inventors: Cheol Ha Lee, Jong Doo Joo, Jung-Han Kim
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Patent number: 7839698Abstract: A semiconductor memory device includes a memory core and an input/output circuit. The memory core amplifies a signal of a memory cell to output the amplified signal through an input/output line pair in a read mode, receives a signal of the input/output line pair to store in the memory cell in a write mode, and electrically separates a bit line pair from the input/output line pair in response to a read column selection signal, a write column selection signal and a first data masking signal. The input/output circuit buffers and provided a signal of the input/output line pair to input/output pins, receives input data from the input/output pins, and buffers the received input data to provide the buffered input data to the input/output line pair. Thus, the semiconductor device can perform a fast data writing operation.Type: GrantFiled: February 20, 2008Date of Patent: November 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Doo Joo, Cheol-Ha Lee, Jung-Han Kim
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Publication number: 20100182852Abstract: An oscillation circuit includes an internal voltage generator and an oscillator. The internal voltage generator receives an external voltage and generates an internal voltage based on the external voltage. The internal voltage varies in linearly with an operational temperature. The oscillator generates a variable oscillation signal based on the internal voltage. A period of the variable oscillation signal varies in linearly with the operational temperature.Type: ApplicationFiled: January 19, 2010Publication date: July 22, 2010Inventors: Jong-Doo Joo, Cheol-Ha Lee, Sang-Seok Lee
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Publication number: 20090261892Abstract: An active charge pump circuit may include a charge pump circuit, a control circuit, and a charge transfer circuit. The charge pump circuit may generate a charge pumping voltage in response to an active enable signal. The control circuit may generate a charge transfer control signal varying between a ground voltage and a boosted power supply voltage that is twice as much as a power supply voltage in response to the active enable signal. The charge transfer circuit may output the charge pumping voltage as an active voltage in response to the charge transfer control signal.Type: ApplicationFiled: April 7, 2009Publication date: October 22, 2009Inventor: Jong-Doo Joo
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Patent number: 7518943Abstract: An embedded memory and methods thereof are provided. The example embedded memory may include a first memory block configured to output data, selected by a first column select signal, on a first scan output line if the first memory block is determined to be non-defective and a second memory block configured to output data, selected by a second column select signal on a second scan output line if the first memory block is determined to be non-defective, the second memory block further configured to output data, selected by the first column select signal, on the first scan output line if the first memory block is determined to be defective.Type: GrantFiled: December 26, 2006Date of Patent: April 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Doo Joo, Cheol-Ha Lee
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Publication number: 20080291756Abstract: A semiconductor memory device includes a memory core and an input/output circuit. The memory core amplifies a signal of a memory cell to output the amplified signal through an input/output line pair in a read mode, receives a signal of the input/output line pair to store in the memory cell in a write mode, and electrically separates a bit line pair from the input/output line pair in response to a read column selection signal, a write column selection signal and a first data masking signal. The input/output circuit buffers and provided a signal of the input/output line pair to input/output pins, receives input data from the input/output pins, and buffers the received input data to provide the buffered input data to the input/output line pair. Thus, the semiconductor device can perform a fast data writing operation.Type: ApplicationFiled: February 20, 2008Publication date: November 27, 2008Applicant: Samsung Electronics Co. Ltd.Inventors: Jong-Doo Joo, Cheol-Ha Lee, Jung-Han Kim
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Patent number: 7269076Abstract: A low power consumption data input/output circuit and method includes input/output lines, bit line sense amplifying unit groups, and data input/output units. Each pair of the input/output lines is arranged in each sub memory cell block. The bit line sense amplifying unit groups are connected between the sub memory cell blocks and the pairs of input/output lines and mutually transmit data signals between the sub memory cell blocks and the pairs of input/output lines in response to first control signals. Each data input/output unit is connected to each of input/output line groups each including a first predetermined number of input/output line pairs, selects as a data output path some of the input/output lines included in each input/output line group, pre-discharges the residual input/output lines to a ground voltage, and receives and transmits the data signals to the cell blocks via the selected input/output lines.Type: GrantFiled: June 23, 2004Date of Patent: September 11, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-doo Joo, Gyu-hong Kim
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Publication number: 20070201289Abstract: An embedded memory and methods thereof are provided. The example embedded memory may include a first memory block configured to output data, selected by a first column select signal, on a first scan output line if the first memory block is determined to be non-defective and a second memory block configured to output data, selected by a second column select signal on a second scan output line if the first memory block is determined to be non-defective, the second memory block further configured to output data, selected by the first column select signal, on the first scan output line if the first memory block is determined to be defective.Type: ApplicationFiled: December 26, 2006Publication date: August 30, 2007Inventors: Jong-Doo Joo, Cheol-Ha Lee
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Patent number: 7079435Abstract: A sense amplifier includes: a bit line and a complementary bit line; a data input/output line and a complementary data input/output line; first and second transistors which are connected in series between the data input/output line and the bit line; and third and fourth transistors which are connected in series between the complementary data input/output line and the complementary bit line, where the gate of the first transistor is connected to the complementary data input/output line, the gate of the third transistor is connected to the data input/output line, and a write column select line enable signal is input to the gates of the second and fourth transistors. Since the sense amplifier can write data before data of adjacent bit line pairs are amplified in a semiconductor memory device, the write timing can be reduced.Type: GrantFiled: October 7, 2004Date of Patent: July 18, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-doo Joo, Gyu-hong Kim
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Patent number: 6918046Abstract: A high speed interface type device can reduce power consumption and a circuit area, and transmit/receive a 4 bit data in one clock period. The high speed interface type device includes a DRAM unit for generating first clock and clock bar signals which do not have a phase difference from a main clock signal, and second clock and clock bar signals having 90° phase difference from the first clock and clock bar signals in a write operation, storing an inputted 4 bit data in one period of the main clock signal according to the first clock to second clock bar signals, synchronizing the stored data with data strobe signals according to the first clock to second clock bar signals in a read operation, and outputting a 4 bit data in one period of the main clock signal, and a controller for transmitting a command, address signal and data signal synchronized with the main clock signal to the DRAM unit in the write operation, and receiving data signals from the DRAM unit in the read operation.Type: GrantFiled: June 1, 2001Date of Patent: July 12, 2005Assignee: Hynix Semiconductor, Inc.Inventors: Yong Jae Park, Jong Doo Joo
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Publication number: 20050083746Abstract: A sense amplifier includes: a bit line and a complementary bit line; a data input/output line and a complementary data input/output line; first and second transistors which are connected in series between the data input/output line and the bit line; and third and fourth transistors which are connected in series between the complementary data input/output line and the complementary bit line, where the gate of the first transistor is connected to the complementary data input/output line, the gate of the third transistor is connected to the data input/output line, and a write column select line enable signal is input to the gates of the second and fourth transistors. Since the sense amplifier can write data before data of adjacent bit line pairs are amplified in a semiconductor memory device, the write timing can be reduced.Type: ApplicationFiled: October 7, 2004Publication date: April 21, 2005Inventors: Jong-doo Joo, Gyu-hong Kim
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Publication number: 20050057976Abstract: Provided are a low power consumption data input/output circuit of an embedded memory device and a data input/output method of the circuit. The embedded memory device includes sub memory cell blocks that share word lines. The data input/output circuit includes input/output lines, bit line sense amplifying unit groups, and data input/output units. Each pair of the input/output lines is arranged in each of the sub memory cell blocks. The bit line sense amplifying unit groups are connected between the sub memory cell blocks and the pairs of input/output lines and mutually transmit data signals between the sub memory cell blocks and the pairs of input/output lines in response to first control signals.Type: ApplicationFiled: June 23, 2004Publication date: March 17, 2005Inventors: Jong-doo Joo, Gyu-hong Kim
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Patent number: 6597614Abstract: A self refresh circuit for a semiconductor memory device can reduce power consumption by varying a self refresh period according to a data holding time of a cell varied by a temperature. The self refresh circuit includes a temperature sensing unit for sensing a temperature, and generating a bias current for adjusting a self refresh period according to a data holding time of a memory cell varied by the temperature, and a ring oscillator unit for generating a pulse signal having a period actively varied according to the temperature by the bias current from the temperature sensing unit.Type: GrantFiled: June 28, 2001Date of Patent: July 22, 2003Assignee: Hynix Semiconductor Inc.Inventors: Jong Ki Nam, Jong Doo Joo