Abstract: As inputs of a controller of a direct current (DC)-DC converter are sampled for a predetermined time and thus two-dimensional state information in which one axis is an input physical quantity and the other axis is a time is generated, the two-dimensional state information is processed by a convolutional neural network to determine and output one of a plurality of control signals. An artificial intelligence control part may operate in accordance with a plurality of operation conditions or dynamically determined operation conditions by applying different artificial intelligence engines according to operation modes.

Abstract: A semiconductor device includes, first and second source/drain patterns on an active pattern and spaced apart from each other, a first source/drain contact on the first source/drain pattern and including a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, a second source/drain contact on the second source/drain pattern, and a gate structure on the active pattern between the first and second source/drain contacts and including a gate electrode, wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, and a height from a top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film.

Abstract: The present invention discloses a charge trap flash memory cell with multi-doped layers at the active region, a memory array using of the memory cell, and an operating method of the same. The charge trap memory cell structure of the present invention is characterized by forming multi-doped layers at the active region appropriately, and it is a difference from the conventional art. The present invention induces electrons to band-to-band tunnel at the PN junction with the source/drain region by the multi-doped layers, and accelerates the electrons at the reverse bias to generate an avalanche phenomenon. Therefore, the method for operating a memory array of the present invention comprises programming by injecting holes which are generated by the avalanche phenomenon into multi-dielectric layers of each memory cells, and erasing by injecting electrons through an F-N tunneling from channels into the multi-dielectric layers of each memory cells.

Abstract: A dynamic random access memory (DRAM) device has dual-gate vertical channel transistors. The device is comprised of pillar-shaped active patterns including source regions contacting with a semiconductor substrate, drain regions formed over the drain regions, and channel regions formed between the source and drain regions. The active patterns are disposed in a cell array field. On the active patterns, bit lines are arranged to connect the drain regions along a direction. Between the active patterns, word lines are arranged intersecting the bit lines. Gat insulation films are interposed between the word lines and active patterns.

Abstract: A twin-ONO-type SONOS memory includes a semiconductor substrate having a source region, a drain region and a channel region between the source and drain regions, twin silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layers, a first ONO dielectric layer being on the channel region and the source region and as second ONO dielectric layer being on the channel region and the drain region, and a control gate on the channel region, between the twin ONO dielectric layers, the twin ONO dielectric layers extending along at least lower lateral sides of the control gate adjacent the channel region, wherein the twin ONO dielectric layers extend towards the source and drain regions further than the control gate.

Abstract: Provided are a silicon/oxide/nitride/oxide/silicon (SONOS) memory, a fabricating method thereof, and a memory programming method. The SONOS memory includes a substrate; a first insulating layer stacked on the substrate; a semiconductor layer, which is patterned on the first insulating layer in a predetermined shape, including source and drain electrodes separated by a predetermined interval; a second insulating layer located on the semiconductor layer between the source and drain electrodes; a memory layer, which is deposited on sides of a portion of the semiconductor layer between the source and drain electrodes and on sides and an upper surface of the second insulating layer, including electron transferring channels and an electron storing layer; and a gate electrode, which is deposited on a surface of the memory layer, for controlling transfer of electrons in the memory layer. The programming method may provide a large capacity, stable, multi-level memory.

Abstract: A silicon controlled rectifier (SCR) may include a first well and a second well formed within a substrate. A first junction region and a second junction region may be formed within the first well. A third junction region may include a first portion formed within the first well and a second portion formed within the substrate. A fourth junction region may include a first portion formed within the second well and a second portion formed within the substrate. A gate electrode may be formed on the substrate between the third junction region and the fourth junction region. A fifth junction region may be formed within a region of the substrate.

Abstract: A dynamic random access memory (DRAM) device has dual-gate vertical channel transistors. The device is comprised of pillar-shaped active patterns including source regions contacting with a semiconductor substrate, drain regions formed over the drain regions, and channel regions formed between the source and drain regions. The active patterns are disposed in a cell array field. On the active patterns, bit lines are arranged to connect the drain regions along a direction. Between the active patterns, word lines are arranged intersecting the bit lines. Gat insulation films are interposed between the word lines and active patterns.

Abstract: A twin-ONO-type SONOS memory includes a semiconductor substrate having a source region, a drain region and a channel region between the source and drain regions, twin silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layers, a first ONO dielectric layer being on the channel region and the source region and as second ONO dielectric layer being on the channel region and the drain region, and a control gate on the channel region, between the twin ONO dielectric layers, the twin ONO dielectric layers extending along at least lower lateral sides of the control gate adjacent the channel region, wherein the twin ONO dielectric layers extend towards the source and drain regions further than the control gate.

Abstract: A method of manufacturing a twin-ONO-type SONOS memory using a reverse self-alignment process, wherein an ONO dielectric layer is formed under a gate and physically separated into two portions using a reverse self-alignment process irrespective of photolithographic limits. To facilitate the reverse self-alignment, a buffer layer and spacers for defining the width of the ONO dielectric layer are adopted. Thus, the dispersion of trapped charges during programming and erasing can be appropriately adjusted, thus improving the characteristics of the SONOS. The present invention prevents the redistribution of charges in time after the programming and erasing operations.

Abstract: A method of manufacturing a twin-ONO-type SONOS memory using a reverse self-alignment process, wherein an ONO dielectric layer is formed under a gate and physically separated into two portions using a reverse self-alignment process irrespective of photolithographic limits. To facilitate the reverse self-alignment, a buffer layer and spacers for defining the width of the ONO dielectric layer are adopted. Thus, the dispersion of trapped charges during programming and erasing can be appropriately adjusted, thus improving the characteristics of the SONOS. The present invention prevents the redistribution of charges in time after the programming and erasing operations.

Abstract: The present invention relates to a method for fabricating semiconductor device with negative differential conductance or transconductance. According to the present invention, a fabrication process thereof can be simplified by using an SOI (Silicon-On-Insulator) substrate, and a tunneling device exhibiting the negative differential conductance or transconductance at room temperature can be implemented by using P+-N+ junction barriers as tunneling barriers and implanting impurity ions into a channel region so that their density is higher than the effective density of states where electrons or holes can exist thereon. Since the semiconductor device with the negative differential conductance or transconductance can be also be implemented even at room temperature, there is an advantage in that the present invention can be applied to an SRAM or a logic device using a device which can be turned on/off in response to a specific voltage. Further, according to the fabrication method of the present invention.

Abstract: The present invention relates to a method for fabricating semiconductor device with negative differential conductance or transconductance. According to the present invention, a fabrication process thereof can be simplified by using an SOI (Silicon-On-Insulator) substrate, and a tunneling device exhibiting the negative differential conductance or transconductance at room temperature can be implemented by using P+-N+ junction barriers as tunneling barriers and implanting impurity ions into a channel region so that their density is higher than the effective density of states where electrons or holes can exist thereon. Since the semiconductor device with the negative differential conductance or transconductance can be also be implemented even at room temperature, there is an advantage in that the present invention can be applied to an SRAM or a logic device using a device which can be turned on/off in response to a specific voltage.

Abstract: Provided are a silicon/oxide/nitride/oxide/silicon (SONOS) memory, a fabricating method thereof, and a memory programming method. The SONOS memory includes a substrate; a first insulating layer stacked on the substrate; a semiconductor layer, which is patterned on the first insulating layer in a predetermined shape, including source and drain electrodes separated by a predetermined interval; a second insulating layer located on the semiconductor layer between the source and drain electrodes; a memory layer, which is deposited on sides of a portion of the semiconductor layer between the source and drain electrodes and on sides and an upper surface of the second insulating layer, including electron transferring channels and an electron storing layer; and a gate electrode, which is deposited on a surface of the memory layer, for controlling transfer of electrons in the memory layer. The programming method may provide a large capacity, stable, multi-level memory.

Abstract: The present invention provides methods for manufacturing field emitter arrays on a silicon-on-insulator (SOI) wafer, one of which comprising steps of forming a doped silicon layer by doping a dopant on a single crystalline silicon layer of an SOI wafer; making a buffer oxide layer on the doped silicon layer; making a stripe pattern of silicon nitride on the buffer oxide layer; etching the buffer oxide layer using the stripe pattern as a mask; etching the doped silicon layer anisotropically using the stripe pattern as a mask; making a minute mask pattern of silicon nitride on the buffer oxide layer by patterning the stripe pattern of silicon nitride; selectively oxidizing the upper part of the doped silicon layer to form an oxide layer except on the portions under the mask pattern; etching away the mask pattern of silicon nitride and the buffer oxide layer deposited under the mask pattern; etching away the exposed doped silicon layer for making gate holes of undercut shape; forming metal layers on the SOI wafe

Abstract: The present invention is directed to fabricating a MOSFET-controlled FEA, in which the emitter array and the cathode electrode are separated and connected to each other by a MOSFET, the cathode electrode and the n-well beneath the emitter array thereby being used as a source and a drain of the MOSFET.

Abstract: A method for preparing spherical phosphor particles is disclosed, wherein a precursor solution of phosphors is decomposed to solid particles by aerosol pyrolysis and rapid cooling and subsequently the solid particles are heat-treated at a temperature of 1000.degree. C. to 1600.degree. C. for a period of 1 hour to 9 hours.

Abstract: The present invention provides field emitter arrays (FEAs) having incorporated with metal oxide semiconductor field effect transistors (MOSFETs) and method for fabricating the same which realizes a simultaneous fabrication of two kinds of devices, namely, the FEA and MOSFETs, by using common processing steps among the processes of fabricating the Si-FEA or the metal FEA and the MOSFETs, wherein the method comprises steps of forming field emission tips and active regions for MOSFETs by oxidizing selected portions of the silicon nitride layer, forming a gate insulating oxide layers for the FEA and field oxide layers for MOSFETs simultaneously by the LOCOS method and connecting gate electrodes(row line) and cathode electrodes(column line) of the FEA to MOSFETs.

Abstract: The present invention privides a method for manufacturing an ISRC MOSFET, comprising steps of forming an isolating layer through the LOCOS process, depositing a mask oxide layer, exposing only the part of silicon substrate for forming the channel and shallow junction of source/drain layers, depositing the first nitride layer over the resultant substrate, dry-etching the first nitride layer to form a nitride side-wall, forming an oxide layer being recessed into the channel, wet-etching the nitride side-wall, forming two doped layers for the shallow source/drain by an N.sup.+ or P.sup.+ ion-implantation, depositing the second nitride layer, dry-etching for forming a nitride side-wall, forming a P.sup.- or N.sup.- doped layer between the two doped layers, forming a gate oxide layer on the P.sup.- or N.sup.

Abstract: The present invention provides field emitter arrays (FEAs) incorporated with metal oxide semiconductor field effect transistors (MOSFETs) and method for fabricating the same which realizes a simultaneous fabrication of two kinds of devices, namely, an FEA and MOSFETs, by using common processing steps among the processes of fabricating Si-FEAs or metal FEAs and MOSFETs, wherein the method comprises steps of forming field emission tips and active regions for MOSFETs by oxidizing selected portions of a silicon nitride layer, forming a gate insulating oxide layer for the FEA and field oxide layers for MOSFETs simultaneously by the LOGOS method and connecting gate electrodes (row line) and cathode electrodes (column line) of the FEA to MOSFETs.