Abstract: Provided is a synaptic array structure. The synaptic array structure includes: an isolation insulating layer positioned in a predetermined area on a semiconductor substrate to isolate devices; TFT-type synaptic devices arranged in an array on an isolation insulating layer; and CMOS peripheral circuits provided on the semiconductor substrate. The TFT-type synaptic device includes: a source and a drain positioned on the isolation insulating layer; a semiconductor body positioned between the source and the drain; oxide layers positioned between the semiconductor body and the source/drain; a semiconductor layer for channel; a TFT gate insulating layer; and a TFT gate electrode. The present invention, based on CMOS integration technology, processes TFT-type synaptic devices and CMOS peripheral circuits together, thereby reducing the number of masks and fabrication steps used during the fabricating process.

Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on a winding axis to define a core and an outer circumference. The first electrode includes a first active material portion coated with an active material layer and a first uncoated portion not coated with an active material layer along a winding direction. At least a part of the first uncoated portion is defined as an electrode tab by itself. The first uncoated portion includes a first portion adjacent to the core of the electrode assembly, a second portion adjacent to the outer circumference of the electrode assembly, and a third portion interposed between the first portion and the second portion. The first portion or the second portion has a smaller height than the third portion in the winding axis direction.

Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on an axis to define a core and an outer circumference. The first electrode includes an uncoated portion at a long side end thereof and exposed out of the separator along a winding axis direction of the electrode assembly. A part of the uncoated portion is bent in a radial direction of the electrode assembly to form a bending surface region that includes overlapping layers of the uncoated portion, and in a partial region of the bending surface region, the number of stacked layers of the uncoated portion is 10 or more in the winding axis direction of the electrode assembly.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.

Abstract: A suspension for a vehicle provides a configuration in which a bolt is screw-fastened to a stud part of a ball joint in a state in which the stud part is inserted into a knuckle, an outer diameter of the stud part is increased at the time of fastening the bolt so that the stud part and the knuckle are coupled to each other. Thus, a position of a hard point corresponding to a center of the ball joint is not changed when the ball joint is coupled by the bolt.

Abstract: The embodiments of the present disclosure relate to a radar control device and method. Specifically, a radar control device according to the present disclosure may include a receiver configured to receive vehicle surrounding information about surroundings of a host vehicle from a radar sensor, a map generator configured to determine a measurement value of the radar sensor for an object from the vehicle surrounding information, determine a detection probability for the measurement value, and generate a predicted occupancy probability grid map based on the detection probability, and a determiner configured to determine a free space in which the host vehicle can travel based on the predicted occupancy probability grid map.

Abstract: The present invention relates to a vessel data integration system and a vessel comprising same. Accordingly, the present invention preferably comprises: a first vessel data conversion device for converting first vessel data which have a non-standard format and are received from first equipment; a second vessel data conversion device for converting second vessel data which have a standard format and are received from second equipment; a data processing device for classifying, by type, the integrated vessel data received from the vessel data conversion device; a complex event processing (CEP) device for filtering out integrated vessel data, which needs to be transmitted in real-time; and a real-time data transmission device for transmitting in real-time the integrated vessel data.

Abstract: The present invention relates to a ship data consolidated management method and a device for same. Accordingly, the present invention relates to a ship data consolidated management method and device, the method being characterized by comprising the steps of: collecting ship data from at least one piece of ship equipment; converting the ship data to a certain data format; and transmitting the converted ship data to an external device.

Abstract: The present invention relates to a vessel data integration system and a vessel comprising same. Accordingly, the present invention preferably comprises: a first vessel data conversion device for converting first vessel data which have a non-standard format and are received from first equipment into integrated vessel data by using a vessel data model (VDM)-based VDM path; and a second vessel data conversion device for converting second vessel data which have a standard format and are received from second equipment into the integrated vessel data.

Abstract: The present invention relates to a vessel data integration system and a vessel comprising same. According to the present invention, a vessel data request including a VDM path is received, and by using the received VDM path, the requested vessel data is searched from a database in which vessel data are stored. The VDM path may be an identifier hierarchically defining paths leading to each vessel data in a VDM, and each vessel data may be identified by the VDM path. Accordingly, necessary vessel data may be efficiently provided to various third-party services.

Abstract: The present invention relates to a vessel data integration system and a vessel comprising same. Accordingly, the present invention preferably comprises: a first vessel data conversion device for converting first vessel data which have a non-standard format and are received from first equipment into integrated vessel data by using a vessel data model (VDM)-based VDM path; and a second vessel data conversion device for converting second vessel data which have a standard format and are received from second equipment into the integrated vessel data.

Abstract: The present invention relates to a method for collecting vessel data using a vessel data model (VDM), a device for collecting vessel data, and a vessel comprising same. Accordingly, it is preferable that the present invention comprises the steps of: acquiring vessel data generated from vessel equipment; and, on the basis of a VDM, converting the vessel data into integrated vessel data having an integrated format, and collecting same, wherein the VDM is generated by combining a vessel model, a system model and a data model, wherein the vessel model is a model defined by hierarchically classifying the vessel equipment, the system model is a model defined by structuring the vessel data, and the data model is a model for defining the attributes and types of the vessel data.

Abstract: The present invention relates to a vessel data integration system and a vessel comprising same. Accordingly, the present invention preferably comprises: a first vessel data conversion device for converting first vessel data which have a non-standard format and are received from first equipment; a second vessel data conversion device for converting second vessel data which have a standard format and are received from second equipment; a data processing device for classifying, by type, the integrated vessel data received from the vessel data conversion device; a complex event processing (CEP) device for filtering out integrated vessel data, which needs to be transmitted in real-time; and a real-time data transmission device for transmitting in real-time the integrated vessel data.

Abstract: The present invention relates to a ship data consolidated management method and a device for same. Accordingly, the present invention relates to a ship data consolidated management method and device, the method being characterized by comprising the steps of: collecting ship data from at least one piece of ship equipment; converting the ship data to a certain data format; and transmitting the converted ship data to an external device.

Abstract: The present invention relates to a test equipment of a chip memory device. A memory pattern test is implemented using a pattern generation substrate in which a processor is designed in an EPLD for thereby implementing a PC test and pattern programming, so that a test evaluated under a PC environment formed of a CPU and chip sets. Two processes of a chip device test and automatic test are performed in one equipment using a generated test pattern. The PC test and automatic test are separated using a high speed switching device which is capable of implementing a conversion without a signal distortion between the signal lines extended from the chip sets and the pattern generation substrate. Therefore, in the present invention, it is possible to enhance a test performance and decrease the test time and error ratio and cost of the products.

Abstract: The present invention relates to a test equipment of a chip memory device. A memory pattern test is implemented using a pattern generation substrate in which a processor is designed in an EPLD for thereby implementing a PC test and pattern programming, so that a test evaluated under a PC environment formed of a CPU and chip sets. Two processes of a chip device test and automatic test are performed in one equipment using a generated test pattern. The PC test and automatic test are separated using a high speed switching device which is capable of implementing a conversion without a signal distortion between the signal lines extended from the chip sets and the pattern generation substrate. Therefore, in the present invention, it is possible to enhance a test performance and decrease the test time and error ratio and cost of the products.