Abstract: A chemical mechanical polishing machine includes a polishing head assembly including a polishing head body and a membrane disposed at a bottom of the polishing head body. The bottom surface of the membrane includes a hydrophobic area and a hydrophilic area.

Abstract: A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.

Abstract: A wafer boat assembly including a boat, a pedestal, and a base. The boat includes a slot to hold a wafer and a rod including a gas line. The pedestal includes a first surface and a connection line coupled to the gas line. The base is on a second surface of the pedestal, rotates the pedestal, and supplies gas to the connection line. The boat is on the first surface of the pedestal. The gas flows along the gas line and is dispensed from a location where the rod contacts the wafer to levitate the wafer.

Abstract: A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.

Abstract: A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.

Abstract: A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.

Abstract: A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.

Abstract: A chemical mechanical polishing machine includes a polishing head assembly including a polishing head body and a membrane disposed at a bottom of the polishing head body. The bottom surface of the membrane includes a hydrophobic area and a hydrophilic area.

Abstract: A chemical mechanical polishing machine includes a polishing head assembly including a polishing head body and a membrane disposed at a bottom of the polishing head body. The bottom surface of the membrane includes a hydrophobic area and a hydrophilic area.

Abstract: A method of manufacturing a vertical-cell-type semiconductor device may include stacking alternately first insulating layers and second insulating layers on a substrate, forming a channel hole through the first and second insulating layers, and forming dielectric layers. A channel layer and a gap fill pattern may be formed within the channel hole. The channel layer may cover a top surface of an uppermost first insulating layer. The top surface of the gap fill pattern is at the same level with the top surface of the channel layer. A first conductivity type impurities may be implanted into the channel layer to form a channel impurity region. A top surface of the gap fill pattern may be recessed. A contact pad on the recessed surface of the gap fill pattern may be formed. A ground selection gate electrode, cell gate electrodes, and string selection gate electrodes may be formed in interlayer spaces that be formed by removing the second insulating layers.

Abstract: According to example embodiments of inventive concepts, a non-volatile memory device includes a substrate including a second impurity region crossing a first impurity region, and channel regions extending in a vertical direction on the substrate. Gate electrodes may be separated from each other in a vertical direction and a horizontal direction along outer walls of the channel regions. A first insulating interlayer may be on the gate electrodes and the channel regions, where the first insulating interlayer defines a contact hole between at least one adjacent pair gate electrodes and a contact plug is formed in the contact hole to be electrically connected to the second impurity region. An etch stop layer pattern may be on the contact plug and the first insulating interlayer.

Abstract: Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.

Abstract: A chemical mechanical polishing machine includes a polishing head assembly including a polishing head body and a membrane disposed at a bottom of the polishing head body. The bottom surface of the membrane includes a hydrophobic area and a hydrophilic area.

Abstract: A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.

Abstract: A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.

Abstract: According to example embodiments of inventive concepts, a non-volatile memory device includes a substrate including a second impurity region crossing a first impurity region, and channel regions extending in a vertical direction on the substrate. Gate electrodes may be separated from each other in a vertical direction and a horizontal direction along outer walls of the channel regions. A first insulating interlayer may be on the gate electrodes and the channel regions, where the first insulating interlayer defines a contact hole between at least one adjacent pair gate electrodes and a contact plug is formed in the contact hole to be electrically connected to the second impurity region. An etch stop layer pattern may be on the contact plug and the first insulating interlayer.

Abstract: A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of preliminary gate structures, forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures, and forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed therebetween. The method also includes removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, and a lower portion of the capping layer pattern remains on lower sidewalls of the preliminary gate structures. The method further includes forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures, reacting the conductive layer with the preliminary gate structures, and forming an insulation layer having an air gap therein.

Abstract: Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.

Abstract: A method of fabricating a three-dimensional semiconductor memory device includes providing a substrate which includes a cell array region and a peripheral region. The method further includes a peripheral structure on the peripheral region of the substrate, where the peripheral structure includes peripheral circuits and is configured to expose the cell array region of the substrate. The method further includes forming a lower cell structure on the cell array region of the substrate, forming an insulating layer to cover the peripheral structure and the lower cell structure on the substrate, planarizing the insulating layer using top surfaces of the peripheral structure and the lower cell structure as a planarization stop layer, and forming an upper cell structure on the lower cell structure.