Abstract: Provided are a transmitter and a method for transmitting a data block in a wireless communication system. The method comprises the following steps: deciding the number of bits (s) and encoders (NES) to allocate to one axis of a signal constellation; encoding an information bit based on the s and the NES and generating a coded block; parsing the coded block based on the s and the NES and generating a plurality of frequency sub-blocks; and transmitting the plurality of frequency sub-blocks to a receiver.

Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.

Abstract: A multilayer capacitor includes a body including dielectric layers and internal electrodes and external electrodes disposed on an external surface of the body and connected to the internal electrodes. The body includes a first surface and a second surface to which the internal electrodes are exposed, the first surface and the second surface opposing each other in a first direction, a third surface and a fourth surface opposing each other in a second direction which is a direction in which the dielectric layers are stacked, and a fifth surface and a sixth surface opposing each other in a third direction. At least one of the internal electrodes include a first bottleneck structure having a first directional length of a third-directional outer region smaller than an inner region thereof and a second bottleneck structure having a third directional length of a first directional outer region smaller than an inner region thereof.

Abstract: Disclosed is an electronic device configured to perform a secure boot. The electronic device according to an embodiment disclosed herein may include: a first memory area for storing a firmware signed with a private key; a second memory area for storing a boot loader configured to verify integrity of the firmware and executing the firmware of which integrity has been verified; and a third memory area for storing a first public key paired with the private key, wherein the second memory area may store a second public key paired with the private key. The boot loader may verify the integrity of the firmware with the first public key when there is the first public key in the third memory area and verify the integrity of the firmware with the second public key when there is no first public key is in the third memory area.

Abstract: A vertical NAND flash type semiconductor device may include a plurality of cell strings extending vertically, each of the plurality of cell strings including a plurality of cells connected in series vertically. The plurality of cells in each cell strings include a plurality of effective cells for data storage and a plurality of compensation cells for resistance compensation. In each cell string, a change in a string resistance of the cell string that may occur due to a change of resistance states of the plurality of effective cells of that cell string may be controlled by controlling resistance states of the plurality of compensation cells of that cell string according to the resistance states of the plurality of effective cells in that cell string.

Abstract: The present invention relates to a method for purification of hemopexin and haptoglobin and provides a method in which a solution containing hemopexin and haptoglobin is titrated to a range of specific pH values without a step of precipitating haptoglobin by salt addition, followed by separating and purifying hemopexin and haptoglobin individually.

Abstract: A multilayer capacitor includes: a capacitor body including first and second internal electrodes alternately stacked with a dielectric layer interposed therebetween, and having first to six surfaces, the first internal electrode being exposed through the third, fifth, and sixth surfaces, the second internal electrode being exposed through the fourth, fifth, and sixth surfaces; first and second side portions disposed on the fifth and sixth surfaces of the capacitor body; and first and second external electrodes. The capacitor body includes upper and lower cover portions disposed on an upper surface of an uppermost internal electrode and a lower surfaces of a lowermost internal electrode, respectively, in a stacking direction of the first and second internal electrodes. The first and second side portions and the upper and lower cover portions include zirconium (Zr).

Abstract: Disclosed are a cathode for an all-solid-state battery including a cathode thin film for an all-solid-state battery or a cathode composite membrane for an all-solid-state battery, and an all-solid-state battery including the same. The cathode for an all-solid-state battery contains a grain that has a plane having a low surface energy and has a grain boundary arranged parallel to the electron movement direction, thus effectively lowering the interfacial resistance of the thin film while suppressing the dissolution and diffusion of the transition metal, thereby improving the cycle stability of the all-solid-state battery including the same.

Abstract: A capacitor component includes a body having a lamination portion in which first internal electrodes and second internal electrodes are alternately disposed to face each other in a first direction with dielectric layers disposed therebetween, and first and second margin portions disposed on respective opposing sides of the lamination portion in a second direction perpendicular to the first direction. First and second external electrodes are disposed on respective opposing sides of the body in a third direction and are electrically connected to the first and second internal electrodes, respectively. Each of the first and second margin portions includes a reinforcing pattern.

Abstract: A semiconductor memory device includes a memory cell interposed between a first electrode and a second electrode, and configured with a chalcogenide layer that includes three or more components, and a peripheral circuit for providing the memory cell with a program pulse inducing a compositional gradient in the chalcogenide layer.

Abstract: A capacitor component includes a body having a lamination portion in which first internal electrodes and second internal electrodes are alternately disposed to face each other in a first direction with dielectric layers disposed therebetween, and first and second margin portions disposed on respective opposing sides of the lamination portion in a second direction perpendicular to the first direction. First and second external electrodes are disposed on respective opposing sides of the body in a third direction and are electrically connected to the first and second internal electrodes, respectively. Each of the first and second margin portions includes a reinforcing pattern.

Abstract: A multilayer ceramic capacitor include: a ceramic body including first and second surfaces opposing each other and third and fourth surfaces connecting the first and second surfaces; a plurality of internal electrodes disposed inside the ceramic body and exposed to the first and second surfaces, the plurality internal electrodes each having one end exposed to the third or fourth surface; and first and second side margin portions disposed on sides of the internal electrodes exposed to the first and second surfaces. A dielectric composition of the first and second side margin portions is different from a dielectric composition of the ceramic body, and a dielectric constant of the first and second side margin portions is lower than a dielectric constant of the ceramic body.

Abstract: A multilayer ceramic electronic component includes a body including a dielectric layer, first and second internal electrodes, a stacked portion including first and second surfaces opposing each other in a stacking direction of the first and second internal electrodes, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other, and a coating layer disposed on the first to sixth surfaces of the stacked portion and having first and second connection portions; and first and second external electrodes connected to the first and second internal electrodes, respectively, and arranged on the third and fourth surfaces of the body, wherein the first and second internal electrodes are respectively connected to the first and second external electrodes through the first and second connection portions.

Abstract: A multilayer electronic component includes a body including first and second surfaces opposing each other in the first direction, and third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, a first external electrode including a first base electrode layer including glass and Ni and disposed on the third surface, a first intermediate electrode layer including an alloy containing Sn and Ni and disposed on the first base electrode layer, and a first conductive resin layer including a resin and a metal and disposed on the first intermediate electrode layer and extending to the first and second surfaces, a second external electrode including a second base electrode layer disposed on the fourth surface, a second intermediate electrode layer disposed on the second base electrode layer, and a second conductive resin layer disposed on the second intermediate electrode layer.

Abstract: Provided is a ferroelectric-based synaptic device and a three-dimensional synaptic device stack using the same. The synaptic device includes a source, a drain, a semiconductor body in which a channel region are formed, a gate electrode, and an insulating layer stack disposed between the semiconductor body and the gate electrode. The insulating layer stack includes: a charge trap layer disposed on the channel region of the semiconductor body and is made of a material capable of storing or trapping electric charges; a ferroelectric layer made of a ferroelectric material; and an insulating layer disposed between the charge trap layer and the ferroelectric layer. The synaptic device is characterized in that weight information is volatilely stored in the charge trap layer and non-volatilely stored in the ferroelectric layer.

Abstract: A capacitor component includes a body including dielectric layers, first and second internal electrodes, laminated in a first direction, facing each other, and first and second cover portions, disposed on outermost portions of the first and second internal electrodes, and first and second external electrodes, respectively disposed on both external surfaces of the body in a second direction, perpendicular to the first direction, and respectively connected to the first and second internal electrodes. An indentation including a glass is disposed at at least one of boundaries between the first internal electrodes and the first external electrode or one of boundaries between the second internal electrodes and the second external electrode.

Abstract: A multilayer ceramic capacitor includes a ceramic body having a dielectric layer, a plurality of internal electrodes disposed in the ceramic body, and a first side margin portion and a second side margin portion arranged on end portions of the internal electrodes exposed through respective opposing surfaces of the ceramic body. The ceramic body includes an active portion having the plurality of internal electrodes arranged to overlap each other with the dielectric layer interposed therebetween to form capacitance, and cover portions disposed above an uppermost and below a lowermost internal electrode of the active portion. The first and second side margin portions include tin (Sn), and a content of Sn included in the first and second side margin portions is greater than a content of Sn included in the dielectric layer of the active portion.

Abstract: A multilayer electronic component includes a body including first and second surfaces opposing each other and third and fourth surfaces connected to the first and second surfaces and opposing each other, the body including dielectric layers and internal electrodes interposed between the dielectric layers, and an external electrode disposed on the body to be connected to the internal electrodes. The external electrode includes first and second plating layers respectively covering the third and fourth surfaces, a first electrode layer covering portions of the first and second surfaces and having one side surface in contact with one side surface of the first plating layer, a second electrode layer covering the portions of the first and second surfaces and having one side surface in contact with one side surface of the second plating layer, and third and fourth plating layers respectively covering the first and second plating layers.

Abstract: A multilayer electronic component includes a body including a plurality of internal electrodes and a dielectric layer interposed between the plurality of internal electrodes, and an external electrode including an electrode layer disposed on the body to be connected to the plurality of internal electrodes and a conductive resin layer disposed on the electrode layer. The electrode layer includes an island region.