Abstract: A display device comprises a substrate including a display area and a pad area adjacent to the display area; at least one pad electrode disposed on the substrate in the pad area and connected to the display area; and at least one dummy electrode overlapping the at least one pad electrode and not connected to the display area.

Abstract: A display device includes conductive layers on a substrate, a via layer on the conductive layers, a first electrode and a second electrode extending in one direction on the via layer and spaced from each other, a first insulating layer on the first electrode and the second electrode, a plurality of light emitting elements on the first insulating layer, each of the light emitting elements having one end on the first electrode and an other end on the second electrode, and a first connection electrode and a second connection electrode on the first insulating layer, the first connection electrode overlapping the first electrode, and the second connection electrode overlapping the second electrode, wherein the first connection electrode and the second connection electrode are in contact with the conductive layers through contact portions.

Abstract: Disclosed is an antenna control method and apparatus. The antenna control method includes determining an azimuth angle of an antenna based on ephemeris information of a satellite, determining an elevation angle and a cross level of the antenna based on the azimuth angle and controlling the antenna based on the azimuth angle, the elevation angle, and the cross level.

Abstract: A display device includes: a substrate; a first conductive layer on the substrate and including a conductive pattern electrically connected to a first transistor; a first organic planarization layer on the first conductive layer; an organic layer on the first organic planarization layer and including a first bank having a first height and a second organic planarization layer having a second height lower than the first height; a first electrode on the organic layer; a second electrode on the organic layer and spaced apart from the first electrode; and a light-emitting element between the first electrode and the second electrode. The first organic planarization layer has a first opening exposing the conductive pattern, and the second organic planarization layer has a second opening exposing the conductive pattern. Sidewalls of the first opening and sidewalls of the second opening are not aligned in line with each other.

Abstract: A display device having a pad area and a display area is provided. The display device includes: a substrate; a pad structure on the substrate in the pad area; and a display element part on the substrate in the display area. The pad structure includes a first pad pattern, a second pad pattern on the first pad pattern, and a third pad pattern on the second pad pattern, and the display element part includes a light emitting element configured to emit light in a display direction. The second pad pattern has a first area and a second area, the second pad pattern and the third pad pattern do not contact each other in the first area, and the second pad pattern and the third pad pattern contact each other in the second area.

Abstract: A display device may include a substrate including a display region and a non-display region, the non-display region including a fan-out region and a pad region, a plurality of pixels in the display region, a pad portion located in the pad region, a line portion located in the fan-out region, a power pad portion located in one region of the non-display region, a first power line located in the display region and connected to the plurality of pixels, a second power line located in the display region, spaced from the first power line, and connected to the plurality of pixels, a first bus line located in the non-display region and connected to the first power line, and a second bus line located in the non-display region and connected to the second power line.

Abstract: A display device includes a first electrode group including a plurality of electrodes, a second electrode group spaced apart from the first electrode group in the first direction and including a plurality of electrodes, light-emitting elements disposed on the electrodes spaced apart from one another in the second direction and having a shape extended in the second direction, and connection electrodes. The connection electrodes includes a first connection electrode, a second connection electrode, a third connection electrode, a fourth connection electrode, and the fifth connection electrode, the first connection electrode is spaced apart from a part of the fourth connection electrode disposed on the second electrode group in the first direction, and the second connection electrode is spaced apart from another part of the fourth connection electrode disposed on the first electrode group in the first direction.

Abstract: Disclosed is an antenna control method and apparatus. The antenna control method includes determining an azimuth angle of an antenna based on ephemeris information of a satellite, determining an elevation angle and a cross level of the antenna based on the azimuth angle and controlling the antenna based on the azimuth angle, the elevation angle, and the cross level.

Abstract: The present invention relates to a rotation apparatus of the polarizer for a multiple-polarized satellite signals and a satellite signal receiving apparatus included with the apparatus, includes a feedhorn for receiving satellite; a low noise block down converter for processing signals received by the feedhorn; and a skew compensation apparatus, included in the low noise block down converter or feedhorn, for rotating the low noise block down converter or feedhorn to compensate skew angles in the case that the satellite signals received in the feedhorn are the linearly polarized waves, the low noise block down converter includes the rotation apparatus of the polarizer for receiving linearly polarized signals and circularly polarized signals of the satellite signals, thereby to receive and process both of linearly polarized wave and circularly polarized wave by a simple structure.

Abstract: The present invention relates to a rotation apparatus of the polarizer for a multiple-polarized satellite signals and a satellite signal receiving apparatus included with the apparatus, includes a feedhorn for receiving satellite; a low noise block down converter for processing signals received by the feedhorn; and a skew compensation apparatus, included in the low noise block down converter or feedhorn, for rotating the low noise block down converter or feedhorn to compensate skew angles in the case that the satellite signals received in the feedhorn are the linearly polarized waves, the low noise block down converter includes the rotation apparatus of the polarizer for receiving linearly polarized signals and circularly polarized signals of the satellite signals, thereby to receive and process both of linearly polarized wave and circularly polarized wave by a simple structure.

Abstract: The present invention relates to a TFT array panel and a fabricating method thereof. A gate insulating layer and a passivation layer are formed by printing organic insulating material in order to simplify the fabricating process. The inventive TFT panel includes an insulating substrate, and a gate wire formed on the insulating substrate. The gate wire includes a gate line and a gate pad connected to one end of the gate line. A gate insulating layer is formed on the insulating substrate while exposing the gate pad and a portion of the gate line close to the gate pad. A semiconductor pattern is formed on the gate insulating layer. A data wire is formed on the gate insulating layer. The data wire includes a data line, a source electrode connected to the data line, a drain electrode facing the source electrode and a data pad connected to one end of the data line. A passivation layer is formed on the gate insulating layer while exposing the data pad and a portion of the data line close to the data pad.

Abstract: The present invention relates to a TFT array panel and a fabricating method thereof. A gate insulating layer and a passivation layer are formed by printing organic insulating material in order to simplify the fabricating process. The inventive TFT panel includes an insulating substrate, and a gate wire formed on the insulating substrate. The gate wire includes a gate line and a gate pad connected to one end of the gate line. A gate insulating layer is formed on the insulating substrate while exposing the gate pad and a portion of the gate line close to the gate pad. A semiconductor pattern is formed on the gate insulating layer. A data wire is formed on the gate insulating layer. The data wire includes a data line, a source electrode connected to the data line, a drain electrode facing the source electrode and a data pad connected to one end of the data line. A passivation layer is formed on the gate insulating layer while exposing the data pad and a portion of the data line close to the data pad.

Abstract: The present invention relates to a TFT array panel and a fabricating method thereof. A gate insulating layer and a passivation layer are formed by printing organic insulating material in order to simplify the fabricating process. The inventive TFT panel includes an insulating substrate, and a gate wire formed on the insulating substrate. The gate wire includes a gate line and a gate pad connected to one end of the gate line. A gate insulating layer is formed on the insulating substrate while exposing the gate pad and a portion of the gate line close to the gate pad. A semiconductor pattern is formed on the gate insulating layer. A data wire is formed on the gate insulating layer. The data wire includes a data line, a source electrode connected to the data line, a drain electrode facing the source electrode and a data pad connected to one end of the data line. A passivation layer is formed on the gate insulating layer while exposing the data pad and a portion of the data line close to the data pad.

Abstract: A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a Cr layer are sequentially deposited on a substrate on which a gate wire is formed. Next, the Cr layer is patterned to form a data line, a source electrode and a drain electrode. The doped amorphous silicon layer and the amorphous silicon layer are patterned at the same time, and the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. Subsequently, a passivation layer is deposited and patterned to form a contact hole. An ITO layer is deposited and patterned to form a pixel electrode. According to the present invention, an oxide layer is prevented by performing a sequential deposition of the four layers in a vacuum state. As a result, the on current of the TFT is increased, and HF cleaning is not necessary because no oxide layer is formed. Therefore, the overall TFT manufacturing process is simplified.

Abstract: Disclosed is a satellite tracking antenna applied to a satellite tracking antenna system mounted on a vehicle and method using rotation of a subreflector. The antenna includes a reflector controlled to be oriented toward a target satellite, a subreflector for reflecting a signal reflected from the reflector to an entrance end and for identifying relative signals of upper, lower, left, and right sides of the satellite, a subreflector rotating part for rotating the subreflector at a high RPM, a driving device for driving the reflector in at least one of elevation and azimuth directions, and a fixing member for fixing the antenna system on the vehicle. Thus, since the tracking mechanism is realized by operating the elevation and azimuth motors only using the subreflector, the structure of the antenna can be simplified and the satellite tracking is accurately performed.

Abstract: The present invention relates to a TFT array panel and a fabricating method thereof. A gate insulating layer and a passivation layer are formed by printing organic insulating material in order to simplify the fabricating process. The inventive TFT panel includes an insulating substrate, and a gate wire formed on the insulating substrate. The gate wire includes a gate line extending in a first direction and a gate pad connected to one end of the gate line. A gate insulating layer is formed on the insulating substrate while exposing the gate pad and a portion of the gate line close to the gate pad. A semiconductor pattern is formed on the gate insulating layer. A data wire is formed on the gate insulating layer.

Abstract: A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a Cr layer are sequentially deposited on a substrate on which a gate wire is formed. Next, the Cr layer is patterned to form a data line, a source electrode and a drain electrode. The doped amorphous silicon layer and the amorphous silicon layer are patterned at the same time, and the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. Subsequently, a passivation layer is deposited and patterned to form a contact hole. An ITO layer is deposited and patterned to form a pixel electrode. According to the present invention, an oxide layer is prevented by performing a sequential deposition of the four layers in a vacuum state. As a result, the on current of the TFT is increased, and HF cleaning is not necessary because no oxide layer is formed. Therefore, the overall TFT manufacturing process is simplified.

Abstract: A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a Cr layer are sequentially deposited on a substrate on which a gate wire is formed. Next, the Cr layer is patterned to form a data line, a source electrode and a drain electrode. The doped amorphous silicon layer and the amorphous silicon layer are patterned at the same time, and the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. Subsequently, a passivation layer is deposited and patterned to form a contact hole. An ITO layer is deposited and patterned to form a pixel electrode. According to the present invention, an oxide layer is prevented by performing a sequential deposition of the four layers in a vacuum state. As a result, the on current of the TFT is increased, and HF cleaning is not necessary because no oxide layer is formed. Therefore, the overall TFT manufacturing process is simplified.

Abstract: A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a Cr layer are sequentially deposited on a substrate on which a gate wire is formed. Next, the Cr layer is patterned to form a data line, a source electrode and a drain electrode. The doped amorphous silicon layer and the amorphous silicon layer are patterned at the same time, and the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. Subsequently, a passivation layer is deposited and patterned to form a contact hole. An ITO layer is deposited and patterned to form a pixel electrode. According to the present invention, an oxide layer is prevented by performing a sequential deposition of the four layers in a vacuum state. As a result, the on current of the TFT is increased, and HF cleaning is not necessary because no oxide layer is formed. Therefore, the overall TFT manufacturing process is simplified.

Abstract: A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a Cr layer are sequentially deposited on a substrate on which a gate wire is formed. Next, the Cr layer is patterned to form a data line, a source electrode and a drain electrode. The doped amorphous silicon layer and the amorphous silicon layer are patterned at the same time, and the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. Subsequently, a passivation layer is deposited and patterned to form a contact hole. An ITO layer is deposited and patterned to form a pixel electrode. According to the present invention, an oxide layer is prevented by performing a sequential deposition of the four layers in a vacuum state. As a result, the on current of the TFT is increased, and HF cleaning is not necessary because no oxide layer is formed. Therefore, the overall TFT manufacturing process is simplified.