Abstract: System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing a key process on a sample number of wafers of a lot of wafers; performing a key inline measurement related to the key process to produce metrology data for the wafers; predicting WAT data from the metrology data using an inline-to-WAT model; and using the predicted WAT data to tune a WAT APC process for controlling a tuning process or a process APC process.

Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.

Abstract: A system and method for controlling a dosage profile is disclosed. An embodiment comprises separating a wafer into components of a grid array and assigning each of the grid components a desired dosage profile based upon a test to compensate for topology differences between different regions of the wafer. The desired dosages are decomposed into directional dosage components and the directional dosage components are translated into scanning velocities of the ion beam for an ion implanter. The velocities may be fed into an ion implanter to control the wafer-to-beam velocities and, thereby, control the implantation.

Abstract: System and method for data mining and feature tracking for fab-wide prediction and control are described. One embodiment is a system comprising a database for storing raw wafer manufacturing data; a data mining module for processing the raw wafer manufacturing data to select the best data therefrom in accordance with at least one of a plurality of knowledge-, statistic-, and effect-based processes; and a feature tracking module associated with the data mining module and comprising a self-learning model wherein a sensitivity of the self-learning model is dynamically tuned to meet real-time production circumstances, the feature tracking module receiving the selected data from the data mining module and generating prediction and control data therefrom; wherein the prediction and control data are used to control future processes in the wafer fabrication facility.

Abstract: A method includes providing a plurality of failure dies, and performing a chip probing on the plurality of failure dies to generate a data log comprising electrical characteristics of the plurality of failure dies. An automatic net tracing is performed to trace failure candidate nodes in the failure dies. A failure layer analysis is performed on results obtained from the automatic net tracing. Physical failure analysis (PFA) samples are selected from the plurality of failure dies using results obtained in the step of performing the failure layer analysis.

Abstract: A method for providing a bin ratio forecast at an early stage of integrated circuit device manufacturing processes is disclosed. The method comprises collecting historical data from one or more processed wafer lots; collect measurement data from one or more skew wafer lots; generating an estimated baseline distribution from the collected historical data and collected measurement data; generating an estimated performance distribution based on one or more specified parameters and the generated estimated baseline distribution; determining a bin ratio forecast by applying a bin definition and a yield degradation factor estimation to the generated estimated performance distribution; determining one or more production targets based on the bin ratio forecast; and processing one or more wafers based on the one or more determined production targets.

Abstract: A method of extending advanced process control (APC) models includes constructing an APC model table including APC model parameters of a plurality of products and a plurality of work stations. The APC model table includes empty cells and cells filled with existing APC model parameters. Average APC model parameters of the existing APC model parameters are calculated, and filled into the empty cells as initial values. An iterative calculation is performed to update the empty cells with updated values.

Abstract: In accordance with an embodiment, a method for exception handling comprises accessing an exception type for an exception, filtering historical data based on at least one defined criterion to provide a data train comprising data sets, assigning a weight to each data set, and providing a current control parameter. The data sets each comprise a historical condition and a historical control parameter, and the weight assigned to each data set is based on each historical condition. The current control parameter is provided using the weight and the historical control parameter for each data set.

Abstract: A method for providing bin-based control when manufacturing integrated circuit devices is disclosed. The method comprises performing a plurality of processes on a plurality of wafer lots; determining a required bin quantity, an actual bin quantity, and a projected bin quantity; comparing the determined required bin quantity with the determined actual bin quantity and determined projected bin quantity; and modifying at least one of the plurality of processes on the plurality of wafer lots if the determined actual bin quantity and determined projected bin quantity fail to satisfy the determined required bin quantity.

Abstract: A method of semiconductor fabrication is provided. The method includes providing a model for a device parameter of a wafer as a function of first and second process parameters. The first and second process parameters correspond to different wafer characteristics, respectively. The method includes deriving target values of the first and second process parameters based on a specified target value of the device parameter. The method includes performing a first fabrication process in response to the target value of the first process parameter. The method includes measuring an actual value of the first process parameter thereafter. The method includes updating the model using the actual value of the first process parameter. The method includes deriving a revised target value of the second process parameter using the updated model. The method includes performing a second fabrication process in response to the revised target value of the second process parameter.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes collecting a plurality of manufacturing data sets from a plurality of semiconductor processes, respectively. The method includes normalizing each of the manufacturing data sets in a manner so that statistical differences among the manufacturing data sets are reduced. The method includes establishing a database that includes the normalized manufacturing data sets. The method includes normalizing the database in a manner so that the manufacturing data sets in the normalized database are statistically compatible with a selected one of the manufacturing data sets. The method includes predicting performance of a selected one of the semiconductor processes by using the normalized database. The selected semiconductor process corresponds to the selected manufacturing data set. The method includes controlling a semiconductor processing machine in response to the predicted performance.

Abstract: A method for monitoring overlay of a direct-write system. The method includes providing a substrate having a pattern formed thereon by the direct-write system, generating data associated with the substrate pattern, decomposing the data by applying a transformation matrix, and determining an overlay index based on the decomposed data, the overlay index corresponding to a variation component of the substrate pattern relative to a target pattern.

Abstract: One embodiment is a method for fabricating ICs from a semiconductor wafer. The method includes performing a first process on the semiconductor wafer; taking a first measurement indicative of an accuracy with which the first process was performed; and using the first measurement to generate metrology calibration data, wherein the metrology calibration data includes an effective portion and a non-effective portion. The method further includes removing the non-effective portion from the metrology calibration data and modeling the effective portion with a metrology calibration model; combining the metrology calibration model with a first process model to generate a multi-resolution model, wherein the first process model models an input-output relationship of the first process; and analyzing a response of the multi-resolution model and second measurement data to control performance a second process.

Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes providing product data of a product, the product data including a sensitive product parameter; searching existing products according to the sensitive product parameter to identify a relevant product from the existing products; determining an initial value of a processing model parameter to the product using corresponding data of the relevant product; assigning the initial value of the processing model parameter to a processing model associated with a manufacturing process; thereafter, tuning a processing recipe using the processing model; and performing the manufacturing process to a semiconductor wafer using the processing recipe.

Abstract: The present disclosure describes a semiconductor manufacturing apparatus. The apparatus includes a processing chamber designed to perform a process to a wafer; an electrostatic chuck (E-chuck) configured in the processing chamber and designed to secure the wafer, wherein the E-chuck includes an electrode and a dielectric feature formed on the electrode; a tuning structure designed to hold the E-chuck to the processing chamber by clamping forces, wherein the tuning structure is operable to dynamically adjust the clamping forces; a sensor integrated with the E-chuck and sensitive to the clamping forces; and a process control module for controlling the tuning structure to adjust the clamping forces based on pre-measurement data from the wafer and sensor data from the sensor.

Abstract: A method for providing a bin ratio forecast at an early stage of integrated circuit device manufacturing processes is disclosed. The method comprises collecting historical data from one or more processed wafer lots; collect measurement data from one or more skew wafer lots; generating an estimated baseline distribution from the collected historical data and collected measurement data; generating an estimated performance distribution based on one or more specified parameters and the generated estimated baseline distribution; determining a bin ratio forecast by applying a bin definition and a yield degradation factor estimation to the generated estimated performance distribution; determining one or more production targets based on the bin ratio forecast; and processing one or more wafers based on the one or more determined production targets.

Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes performing a first process to a wafer; measuring the wafer for wafer data after the first process; securing the wafer on an E-chuck in a processing chamber; collecting sensor data from a sensor embedded in the E-chuck; adjusting clamping forces to the E-chuck based on the wafer data and the sensor data; and thereafter performing a second process to the wafer secured on the E-chuck in the processing chamber.

Abstract: A method for monitoring overlay of a direct-write system. The method includes providing a substrate having a pattern formed thereon by the direct-write system, generating data associated with the substrate pattern, decomposing the data by applying a transformation matrix, and determining an overlay index based on the decomposed data, the overlay index corresponding to a variation component of the substrate pattern relative to a target pattern.

Abstract: System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing a key process on a sample number of wafers of a lot of wafers; performing a key inline measurement related to the key process to produce metrology data for the wafers; predicting WAT data from the metrology data using an inline-to-WAT model; and using the predicted WAT data to tune a WAT APC process for controlling a tuning process or a process APC process.

Abstract: A method for providing bin-based control when manufacturing integrated circuit devices is disclosed. The method comprises performing a plurality of processes on a plurality of wafer lots; determining a required bin quantity, an actual bin quantity, and a projected bin quantity; comparing the determined required bin quantity with the determined actual bin quantity and determined projected bin quantity; and modifying at least one of the plurality of processes on the plurality of wafer lots if the determined actual bin quantity and determined projected bin quantity fail to satisfy the determined required bin quantity.