Abstract: A computing system includes host and a storage device. The host includes a host memory and a user interface. The storage device provides the host with a first request including device setting inquiry information, and sets a device configuration based on a first response to the device setting inquiry information received from the host. The host provides the storage device with the first response acquired from a user through the user interface in response to the first request. The device setting inquiry information includes at least one of information on allocation of a map buffer in the host memory, information on allocation of a write buffer in a buffer region of the storage device, or information on a power level of the storage device.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, when updating a target firmware, a memory system may receive, from a host, a temporary firmware for increasing the size of a buffer from a preset first size to a second size equal to or greater than the size of the target firmware, may load and execute the temporary firmware into a processor, may receive the target firmware from the host and write the target firmware to the buffer, and may write the target firmware to the memory device.

Abstract: The present disclosure relates to a display device and an image processing method thereof, and includes a pixel shift processing unit configured to shift an image displayed in an active pixel region within the size of a dummy pixel region. The pixel shift processing unit gradually changes a gray level of at least one dummy pixel in the dummy pixel region adjacent to the active pixel region up to a target gray level of pixel data, and gradually changes a gray level of at least one active pixel of an active pixel adjacent to the dummy pixel region up to a black gray level when the active pixel region is shifted.

Abstract: A dry etching method includes a first step of adsorbing first radicals into a surface of an etching target, wherein the first radicals are contained in first plasma generated from a plasma generator; and a second step of irradiating ion-beams extracted from second plasma generated from the plasma generator onto the surface of the etching target into which the radicals have been adsorbed, thereby desorbing a surface atomic layer of the etching target, wherein the first step is performed such that: a positive potential greater than a potential of the first plasma is applied to one or two selected from first to third grids, while a ground potential is applied to the rest thereof; and a negative potential equal to or lower than a potential of the third grid is applied to a substrate support structure.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may, when setting a firmware as a target firmware, generate a plurality of test commands to test the target firmware, test the target firmware by processing the plurality of test commands, and randomly generate logical block address (LBA) values corresponding to each of the plurality of test commands based on a seed value corresponding to each of the plurality of test commands.

Abstract: The present technology relates to a memory controller and a method of operating the same. The memory controller may include a block manager designating a first memory block as an open block, which is driven to program m-bit data per cell, where m is a natural number, an address manager increasing an access count value corresponding to a logical address for the first memory block whenever a program request or a read request including the logical address is received from a host, and a data manager determining a representative attribute of data programmed in the first memory block based on access count values for the logical addresses for the first memory block when a flush request is received from the host. The block manager may determine whether to designate a new open block according to the determined representative attribute.

Abstract: Memory systems and operating methods of the memory systems are disclosed. In an implementation, a memory system includes a system buffer including buffer areas to which addresses are allocated, and configured to store data in the buffer areas, and a buffer manager configured to designate an address of a buffer area in which a defect occurs as a defect address by comparing a first parity bit for data stored in the system buffer with a second parity bit that is obtained by a computation based on the data stored in the system buffer, and block access to the buffer area designated as the defect address.

Abstract: Embodiments of the present disclosure provide a memory system and an operating method thereof. A memory system includes a memory device and a memory controller. The memory controller is configured to create a bad memory area replacement table including state information of a bad memory area among a plurality of memory areas, add the state information of one or more runtime bad memory areas to the bad memory area replacement table when one or more runtime bad memory areas occur, and remap, based on the bad memory area replacement table, a bad sub-area included in a target memory area to a normal sub-area included in one of remaining bad memory areas other than the target bad memory area among the bad memory areas added to the bad memory area replacement table.

Abstract: This application relates to a method and apparatus for processing a new read-write-operation instruction added to an instruction set to maximize the performance of processing-in-memory (PIM). The read-write-operation instruction performs reading and writing on an operation result of the PIM by returning the operation result of the PIM to a computer system and, at the same time, writing the operation result to a destination address. An instruction processor in PIM includes a response data selector and a finite state machine to process the read-write-operation instruction. The response data selector includes a selector configured to select one of a response data signal and an operation result, and a three-phase buffer configured to allow or disallow response data. The finite state machine of the instruction processor outputs a response permission signal and a response selection signal for controlling the buffer and the selector.

Abstract: The present technology relates to a memory controller and a method of operating the same. The memory controller may include a block manager designating a first memory block as an open block, which is driven to program m-bit data per cell, where m is a natural number, an address manager increasing an access count value corresponding to a logical address for the first memory block whenever a program request or a read request including the logical address is received from a host, and a data manager determining a representative attribute of data programmed in the first memory block based on access count values for the logical addresses for the first memory block when a flush request is received from the host. The block manager may determine whether to designate a new open block according to the determined representative attribute.

Abstract: This application relates to a display stream compression (DSC) encoding method in a DSC encoding hardware device. In one aspect, the method may include applying a DSC encoding setting variable set by a core. The method may also include reading an input video, received through a video receiver, from an image buffer in which the input video is stored. The method may further include receiving a DSC encoding operation execution command from the core and executing a DSC encoding operation on the basis of the DSC encoding setting variable.

Abstract: This application relates to a memory management method for maximizing processing-in-memory (PIM) performance and reducing unnecessary DRAM access time. In one aspect, when processing a PIM instruction packet, an instruction processing unit secondarily processes a request for access to a destination address at which read and write actions of an internal memory are likely to be sequentially performed. By secondarily requesting the destination address, a row address of an open page of the internal memory may match a row address to which a PIM instruction packet processing result is written back. Also, the instruction processing unit inside the PIM maintains memory write and read addresses that have previously requested. The instruction processing unit compares the address of a packet to be processed to the maintained previous memory address and informs a memory controller about the comparison result through a page closing signal.

Abstract: The present disclosure relates to a display device and a driving method thereof, wherein a refresh rate of pixels is controlled at a reference frame frequency in a normal driving mode, and the refresh rate of the pixels is controlled at a frequency lower than the reference frame frequency in a low speed driving mode. In the low speed driving mode, park data is transmitted to a data driving circuit during at least one vertical blank period.

Abstract: Embodiments of the present disclosure provide a memory system and an operating method thereof. A memory system includes a memory device and a memory controller. The memory controller is configured to create a bad memory area replacement table including state information of a bad memory area among a plurality of memory areas, add the state information of one or more runtime bad memory areas to the bad memory area replacement table when one or more runtime bad memory areas occur, and remap, based on the bad memory area replacement table, a bad sub-area included in a target memory area to a normal sub-area included in one of remaining bad memory areas other than the target bad memory area among the bad memory areas added to the bad memory area replacement table.

Abstract: The present disclosure relates to a method for classifying instructions according to the number of operands required for processing-in-memory instruction processing, and a computing device applying same. Efficient instruction processing in a processing-in-memory may include identifying the number of operands required when processing an instruction queuing to be processed, interpreting the instruction queuing to be processed and processing an instruction corresponding to the identified number of required operands. When the number of required operands is 0, the instruction interpretation may interpret the instruction queuing to be processed as a WRITE instruction, and the instruction processing may execute memory writing. When the number of required operands is not 0, the instruction processing may execute memory reading in an internal memory of the processing-in-memory by the same number of times as the number of operands required in the instruction interpreted in the instruction interpretation.

Abstract: The present disclosure relates to a display device and an image processing method thereof, and includes a pixel shift processing unit configured to shift an image displayed in an active pixel region within the size of a dummy pixel region. The pixel shift processing unit gradually changes a gray level of at least one dummy pixel in the dummy pixel region adjacent to the active pixel region up to a target gray level of pixel data, and gradually changes a gray level of at least one active pixel of an active pixel adjacent to the dummy pixel region up to a black gray level when the active pixel region is shifted.

Abstract: A data processing system includes a controller configured to receive a first encoded data item and a write request from a host, the first encoded data item being encoded based on a hamming code. The controller is further configured to store the first encoded data item in a write buffer, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item, encode the first error-corrected data item based on an error correction code to generate a second encoded data item, and transmit the second encoded data item to program the second encoded data item in a non-volatile memory device.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may, when setting a firmware as a target firmware, generate a plurality of test commands to test the target firmware, test the target firmware by processing the plurality of test commands, and randomly generate the logical block address LBA values corresponding to each of the plurality of test commands based on a seed value corresponding to each of the plurality of test commands.

Abstract: This application relates to a method and apparatus for processing a new read-write-operation instruction added to an instruction set to maximize the performance of processing-in-memory (PIM). The read-write-operation instruction performs reading and writing on an operation result of the PIM by returning the operation result of the PIM to a computer system and, at the same time, writing the operation result to a destination address. An instruction processor in PIM includes a response data selector and a finite state machine to process the read-write-operation instruction. The response data selector includes a selector configured to select one of a response data signal and an operation result, and a three-phase buffer configured to allow or disallow response data. The finite state machine of the instruction processor outputs a response permission signal and a response selection signal for controlling the buffer and the selector.

Abstract: This application relates to a memory management method for maximizing processing-in-memory (PIM) performance and reducing unnecessary DRAM access time. In one aspect, when processing a PIM instruction packet, an instruction processing unit secondarily processes a request for access to a destination address at which read and write actions of an internal memory are likely to be sequentially performed. By secondarily requesting the destination address, a row address of an open page of the internal memory may match a row address to which a PIM instruction packet processing result is written back. Also, the instruction processing unit inside the PIM maintains memory write and read addresses that have previously requested. The instruction processing unit compares the address of a packet to be processed to the maintained previous memory address and informs a memory controller about the comparison result through a page closing signal.