Abstract: A scheduling method of a system on chip including a multi-core processor includes receiving a schedule-requested task, converting a priority assigned to the schedule-requested task into a linear priority weight, selecting a plurality of candidate cores, to which the schedule-requested task will be assigned, from among cores of the multi-core processor, calculating a preemption compare index indicating a current load state of each of the plurality of candidate cores, comparing the linear priority weight with the preemption compare index of the each of the plurality of candidate cores to generate a comparison result, and assigning the schedule-requested task to one candidate core of the plurality of candidate cores depending on the comparison result.

Abstract: An application processor including at least one core, at least one first cache respectively connected to the at least one core, the at least one first cache associated with an operation of the at least one core, a second cache associated with an operation of the at least one core, the second cache having a storage capacity greater than the first cache, a cache utilization management circuit configured to generate, a power control signal for power management of the application processor based on a cache hit rate of the second cache; and a power management circuit configured to determine, a power state level of the application processor based on the power control signal and an expected idle time, the power management circuit configured to control the at least one core, the at least one first cache, and the second cache based on the power state level may be provided.

Abstract: A performance boosting method of a semiconductor device includes monitoring input of a user and an amount of system usage, generating user system information in response to an event occurring, the user system information including first information and the amount of system usage, the first information regarding input of the user, adaptively determining a performance boosting target value based on the user system information, and boosting an operating frequency according to the performance boosting target value.

Abstract: There is provided a method of operating a computing device including a processing component based on power consumption. The method includes: obtaining power mode information about the processing component, measuring a temperature of the processing component and a current that flows through the processing component in response to the obtaining the power mode information, generating leakage power information based on the power mode information and the measured temperature and current, and storing the generated leakage power information in a memory.

Abstract: In one example embodiment, an integrated circuit includes a memory configured to store a first table listing a plurality of clip frequencies respectively corresponding to a plurality of reference temperatures, and a second table listing one or more of the plurality of clip frequencies and a plurality of timestamps each respectively corresponding to the one or more of the plurality of clip frequencies. The integrated circuit further includes a cooling frequency adjustor configured to select one of the plurality of clip frequencies stored in the first table as a first clip frequency, and store a current timestamp of the first clip frequency in the second table. The integrated circuit further includes a central processing unit (CPU) configured to control an operation of the cooling frequency adjustor.

Abstract: A power management device includes a workload rate detector configured to adjust a length of a duration period; a power management unit configured to calculate a period workload rate in the duration period; and a voltage-clock provider configured to adjust a power level, based on the period workload rate and/or based on an external command.

Abstract: An application processor includes an application processor including a first processor configured to generate a control signal based on whether user data is changed, wherein the application processor is configured to implement a power manager which dynamically controls power provided to the first processor, in response to the control signal.

Abstract: Provided are multi-core control systems. A multi-core control system includes multiple cores including a first core; and a process dependency recognizer configured to recognize a dependency between processes each executed in the respective cores, wherein if the first core waits for a first period of time to execute a first process, the first core recognizes a process on which the first process depends by the process dependency recognizer.

Abstract: An application processor includes an application processor including a first processor configured to generate a control signal based on whether user data is changed, wherein the application processor is configured to implement a power manager which dynamically controls power provided to the first processor, in response to the control signal.

Abstract: An application processor including at least one core, at least one first cache respectively connected to the at least one core, the at least one first cache associated with an operation of the at least one core, a second cache associated with an operation of the at least one core, the second cache having a storage capacity greater than the first cache, a cache utilization management circuit configured to generate, a power control signal for power management of the application processor based on a cache hit rate of the second cache; and a power management circuit configured to determine, a power state level of the application processor based on the power control signal and an expected idle time, the power management circuit configured to control the at least one core, the at least one first cache, and the second cache based on the power state level may be provided.

Abstract: A system-on-chip includes a symmetric multi-processor including a plurality of cores, each configured to operate in a high performance operating mode and a low performance operating mode. The system-on-chip further includes a clock management unit configured to provide an operating clock signal to the symmetric multi-processor, a state management unit configured to monitor operating states of the cores, a temperature management unit configured to monitor a temperature of the symmetric multi-processor, and a symmetric multi-processor control unit configured to determine the operating clock signal and the operating states of the cores based on a workload of the symmetric multi-processor. The symmetric multi-processor control unit is further configured to differentially determine a maximum operating clock frequency for the cores based on the temperature and the operating states of the cores, which indicate a quantity of cores that are currently in operation.

Abstract: A method of operating a system-on-chip (SOC) including a central processing unit (CPU) and a target hardware to which a dynamic voltage and frequency scaling (DVFS) is applied, includes determining an operating scheme of the target hardware, setting a DVFS application scheme for applying the DVFS to the target hardware, based on the operating scheme of the target hardware, and performing the DVFS on the target hardware, based on the DVFS application scheme.

Abstract: A performance boosting method of a semiconductor device includes monitoring input of a user and an amount of system usage, generating user system information in response to an event occurring, the user system information including first information and the amount of system usage, the first information regarding input of the user, adaptively determining a performance boosting target value based on the user system information, and boosting an operating frequency according to the performance boosting target value.

Abstract: An application processor includes a first core and a second core. The first core is configured to implement a scheduler which monitors a workload of a task of the first core, and the first core is further configured to implement an idle checker which determines whether the second core is idle.

Abstract: A power management device includes a workload rate detector configured to adjust a length of a duration period; a power management unit configured to calculate a period workload rate in the duration period; and a voltage-clock provider configured to adjust a power level, based on the period workload rate and/or based on an external command.

Abstract: A power management device includes a workload rate detector configured to adjust a length of a duration period; a power management unit configured to calculate a period workload rate in the duration period; and a voltage-clock provider configured to adjust a power level, based on the period workload rate and/or based on an external command.

Abstract: In one example embodiment, an integrated circuit includes a memory configured to store a first table listing a plurality of clip frequencies respectively corresponding to a plurality of reference temperatures, and a second table listing one or more of the plurality of clip frequencies and a plurality of timestamps each respectively corresponding to the one or more of the plurality of clip frequencies. The integrated circuit further includes a cooling frequency adjustor configured to select one of the plurality of clip frequencies stored in the first table as a first clip frequency, and store a current timestamp of the first clip frequency in the second table. The integrated circuit further includes a central processing unit (CPU) configured to control an operation of the cooling frequency adjustor.

Abstract: A Dynamic Voltage and Frequency Scaling (DVFS) method, comprising of a scheduling execution of DVFS to adjust frequency or voltage of a target device at a first scheduled time; monitoring operating frequency of the target device; and selectively deferring execution of DVFS at a later scheduled time based on the operating frequency of the target device; wherein execution of DVFS at a next scheduled time is deferred when the operating frequency of the target device is below a given minimum frequency.

Abstract: A method of changing an operating frequency for performing a dynamic voltage and frequency scaling on a central processing unit included in a system on-chip is provided. A previous maximum peak workload of the central processing unit is detected in a history period of the dynamic voltage and frequency scaling when the operating frequency of the central processing unit is determined to be increased, and an increased operating frequency is applied to the central processing unit. The increased operating frequency is calculated based on the previous maximum peak workload of the central processing unit.

Abstract: An application processor includes a first core and a second core. The first core is configured to implement a scheduler which monitors a workload of a task of the first core, and the first core is further configured to implement an idle checker which determines whether the second core is idle.