Abstract: The digital logic level conversion circuit is for converting a small sinusoidal signal or an unbalanced digital signal to a balanced digital signal with 50% duty ratio, and includes an input level shift circuit, two differential amplifiers, an RS flip-flop, a charge-pump circuit, and a bias circuit. The input level shift circuit for AC coupling a sinusoidal wave with a small amplitude (with a minimum of 0.4 Vpp) and converting it into a middle logic level. The two differential amplifiers is used as comparators having hysteresis each other, operates inversely, and outputs digital signals into the RS flip-flop; the bias circuit for controlling a driving current of the differential amplifiers; the RS flip-flop for driving the charge-pump circuit by outputting a digital signal upon receiving outputs from the differential amplifiers; and the charge-pump circuit for generating a reference potential level of the differential amplifiers.

Abstract: A voltage control oscillation circuit for a CMOS which is capable of reducing phase noise and power consumption by adapting a voltage amplitude control loop and a common mode feedback circuit to a conventional LC-tank circuit. The circuit includes an LC-tank oscillation unit for outputting an oscillation voltage, an output common mode feedback unit for receiving an output from the LC-tank oscillation unit and eliminating a common mode noise of the output, and a voltage amplitude control unit for controlling a bias current of the LC-tank oscillation unit in accordance with a voltage difference at both ends of an LC-tank oscillation terminal which voltage is applied thereto through the output common mode feedback unit, for thus controlling the amount of an oscillation voltage.

Abstract: A capacitor type voltage divider circuit is disclosed. The divider has a plurality of reference voltage signals applied from an external source. A plurality of switching sections are provided for switching the reference voltage signals from the source in response to first and second clock signals. A plurality of dividing sections are provided which are each comprised of two capacitors for dividing the voltage signals from the switching section into a predetermined value. With the dividing circuit, precise levels of reference voltage signals are obtained and power consumption is low without an increase in size or lowering of operational speed.

Abstract: Disclosed is a low power-consumption type comparator circuit having two input terminals for receiving two input signals, one of which is an input reference signal and the other of which is an input comparison signal, and two output terminals, the circuit comprising signal converting portion for converting the input signals into current signals, respectively; switching portion for controlling transmission of the current signals to output terminals of the circuit in response to a latch signal indicating a latch operation or a normal operation of the circuit; high level holding portion for maintaining each voltage level of the output terminals to a logical high-state only when the latch operation of the circuit is not performed; amplifying/determining portion for amplifying the current signals and determining logical level of the input comparison signal; and output feedback portion for receiving output signals of the output terminals and enabling to make a current flowing in the circuit to a zero-state, only whi