Abstract: The present invention provides for a register controlled delay locked loop having an acceleration mode for improving accuracy to be correspondent to an increase of the operation speed of a memory device. For this object, in the present intention, the register controlled delay locked loop includes a delay line, a delay model, a delay means, a first and a second phase comparators, a mode decision means, a shift register control means, and a shift register.

Abstract: The present invention discloses a Rambus DRAM which can reduce power consumption by restricting generation of an unnecessary clock by improving command decryption when a command is applied with a COLC packet or COLX packet, so that the other packet cannot influence on another device.

Abstract: A digital DLL apparatus and a method for correcting a duty cycle are disclosed. The digital DLL apparatus for correcting a duty cycle, includes: a buffer for producing a clock input signal; a delay line unit for receiving/delaying the clock input signal and outputting the clock input signal; a blend circuit for bypassing the first clock signal or producing a blended clock signal; a delay model unit for compensating a time difference of an external clock and an internal clock and generating a compensate clock signal; a direct phase detector for generating a first comparison signal; and a phase detector for generating a second comparison signal. The disclosed apparatus can correct the duty error by using the blend circuit and generate an internal clock signal having 50% of duty cycle.

Abstract: A digital DLL apparatus and a method for correcting a duty cycle are disclosed. The apparatus includes: a delay line unit for receiving external clock signal and generating first and second delayed internal clock signals by delaying the external clock signal; a duty error controller for receiving the first and second delayed clock signals and outputting a first duty controlled clock signal and second duty controlled clock signal by shifting edges of the first and second delayed internal clock signals; and a delay model unit for compensating a delay of the duty controlled clock signal by estimating a delay amount of system. The present invention can correct the duty error by using the phase mixer and generate an internal clock signal having 50% of duty cycle.

Abstract: A digital DLL apparatus and a method for correcting a duty cycle are disclosed. The digital DLL apparatus for correcting a duty cycle, includes: a buffer for producing a clock input signal; a delay line unit for receiving/delaying the clock input signal and outputting the clock input signal; a blend circuit for bypassing the first clock signal or producing a blended clock signal; a delay model unit for compensating a time difference of an external clock and an internal clock and generating a compensate clock signal; a direct phase detector for generating a first comparison signal; and a phase detector for generating a second comparison signal. The disclosed apparatus can correct the duty error by using the blend circuit and generate an internal clock signal having 50% of duty cycle.

Abstract: Disclosed is low power type Rambus DRAM including top/bottom memory bank units respectively comprising a plurality of banks for storing data, top and bottom serial/parallel shifter units, an interface logic circuit unit, a delay lock loop (DLL) unit and an input/output block unit. The top serial/parallel shifter unit is connected between the top memory bank unit and the input/output block unit and the bottom serial/parallel shifter unit is connected between the bottom memory bank unit and the input/output block unit. The interface logic circuit unit generates a signal for selecting the top or the bottom memory bank unit according to read or write command received from the external. The DLL unit generates a clock signal according to the signal outputted from the interface logic circuit unit. The input/output block unit generates a signal for selectively controlling the operation of top and bottom serial/parallel shifter units by buffering the clock signal generated from the DLL unit.

Abstract: A clock synchronization circuit using a phase mixer is disclosed. The clock synchronization circuit generates an internal clock signal having a phase between phases of two clock signals generated in two variable delay lines with a predetermined phase difference by using the phase mixer, thereby precisely synchronizing the clock signal. When a shift register for controlling the variable delay line performs a shift operation, the output clock signal from the variable delay line where the shift operation is performed is not inputted to the phase mixer, but the output clock signal from the other variable delay line is inputted to the phase mixer. As a result, jitter elements generated due to the shift operation do not influence the internal clock signal.

Abstract: A clock synchronization circuit. The clock synchronization circuit composed of a digital DLL outputs a clock signal delayed by a variable delay line and a clock signal delayed by an additional delay cell, mixes the two clock signals, and outputs an internal clock signal having a smaller delay than a delay time of a delay cell, thereby rapidly precisely synchronizing an external clock signal and the internal clock signal. In addition, a driving unit and a control unit for adjusting a duty cycle are provided to set up a ratio of 50%, thereby improving operation performance.

Abstract: An apparatus for outputting burst read data is disclosed which divides input data into an odd number data group and an even number data group, selects a data group including a bit to be first outputted and synchronizes the data group including the bit at rising edges of a clock signal and a data group not including the bit at falling edges of a clock signal, thereby continuously outputting burst read data at a high speed according to output mode set in mode register set using sequential or interleave modes.

Abstract: Disclosed is a circuit for controlling output currents of the data ports in a Rambus DRAM having two data ports DQA and DQB. The disclosed circuit arrangements save power and require less chip ‘real estate’ than do known circuit arrangements. First and second current evaluation means output first and second control signals respectively by evaluating currents of the data ports DQA and DQB. A current control value producing means produces a next current control value for the data port DQA by receiving the first control signal and a present current control value of the data port DQA and producing another next current control value for the data port DQB by receiving the second control signal and a present current control value of the data port DQB.

Abstract: Disclosed is low power type Rambus DRAM including top/bottom memory bank units respectively comprising a plurality of banks for storing data, top and bottom serial/parallel shifter units, an interface logic circuit unit, a delay lock loop (DLL) unit and an input/output block unit. The top serial/parallel shifter unit is connected between the top memory bank unit and the input/output block unit and the bottom serial/parallel shifter unit is connected between the bottom memory bank unit and the input/output block unit. The interface logic circuit unit generates a signal for selecting the top or the bottom memory bank unit according to read or write command received from the external. The DLL unit generates a clock signal according to the signal outputted from the interface logic circuit unit. The input/output block unit generates a signal for selectively controlling the operation of top and bottom serial/parallel shifter units by buffering the clock signal generated from the DLL unit.

Abstract: A clock synchronization circuit. The clock synchronization circuit composed of a digital DLL outputs a clock signal delayed by a variable delay line and a clock signal delayed by an additional delay cell, mixes the two clock signals, and outputs an internal clock signal having a smaller delay than a delay time of a delay cell, thereby rapidly precisely synchronizing an external clock signal and the internal clock signal. In addition, a driving unit and a control unit for adjusting a duty cycle are provided to set up a ratio of 50%, thereby improving operation performance.

Abstract: Disclosed is a circuit for controlling output currents of the data ports in a Rambus DRAM having two data ports DQA and DQB. The disclosed circuit arrangements save power and require less chip ‘real estate’ than do known circuit arrangements. First and second current evaluation means output first and second control signals respectively by evaluating currents of the data ports DQA and DQB. A current control value producing means produces a next current control value for the data port DQA by receiving the first control signal and a present current control value of the data port DQA and producing another next current control value for the data port DQB by receiving the second control signal and a present current control value of the data port DQB.

Abstract: A clock control circuit for a Rambus DRAM is provided which reduces power consumption by determining in advance whether an applied command is a read or current control command, and enabling a clock signal for externally outputting an internal data only during the read or current control command.

Abstract: The present invention discloses a Rambus DRAM which can reduce power consumption by restricting generation of an unnecessary clock by improving command decryption when a command is applied with a COLC packet or COLX packet, so that the other packet cannot influence on another device.

Abstract: The present invention relates to a load signal generating circuit of a packet command driving type memory device, in a packet command driving type memory device for generating a load signal for loading data from a core block, a load signal generating circuit of a packet command driving type memory device of the present invention comprises a first signal generating means for receiving a first input signal and generating a first internal signal; a second signal generating means for receiving a second input signal and generating a second internal signal in response to a clock signal; a third signal generating means for receiving a third input signal and generating a third internal signal; a fourth signal generating means for receiving the first internal signal generated from the first signal generating means the second internal signal generated from the second signal generating means as two inputs, selecting and outputting the first internal signal according to the third input signal generated from the third sig